ADG725 Просмотр технического описания (PDF) - Analog Devices

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ADG725

16-/32- Channel, Serially Controlled 4Ω 1.8 V to 5.5 V, ±2.5 V, Analog Multiplexers

Analog Devices 

VDD

0.1␮F

VSS

0.1␮F

VDD

VSS

S

50⍀

D

ADG731*

GND

NETWORK

ANALYZER

50⍀

VS

RL VOUT

50⍀

OFF

ISOLATION

=

20

LOG

VOUT

VS

*SIMILAR CONNECTION FOR ADG725

Test Circuit 8. OFF Isolation

VDD VSS

VDD VSS S1 50⍀

S2

ADG731*

S32

D

GND

NETWORK

ANALYZER

50⍀

VS

RL VOUT

50⍀

*SIMILAR CONNECTION FOR ADG725

VOUT

CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG VS

Test Circuit 9. Channel-to-Channel Crosstalk

VDD

0.1␮F

VSS

0.1␮F

VDD

VSS

S

D

ADG731*

GND

NETWORK

ANALYZER

50⍀

VS

RL VOUT

50⍀

INSERTION LOSS = 20 LOG

VOUT WITH SWITCH

VOUT WITHOUT SWITCH

*SIMILAR CONNECTION FOR ADG725

Test Circuit 10. Bandwidth

ADG725/ADG731

POWER-ON RESET

On power-up of the device, all switches will be in the OFF

condition. The Internal Shift Register is filled with zeros and

will remain so until a valid write takes place.

SERIAL INTERFACE

The ADG725 and ADG731 have a 3-wire serial interface

(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI,

and MICROWIRE interface standards and most DSPs.

Figure 1 shows the timing diagram of a typical write sequence.

Data is written to the 8-bit Shift Register via DIN under the

control of the SYNC and SCLK signals.

When SYNC goes low, the Input Shift Register is enabled. An

8-bit counter is also enabled. Data from DIN is clocked into the

Shift Register on the falling edge of SCLK. Figures 2 and 3

show the contents of the Input Shift Registers for these devices.

When the part has received eight clock cycles after SYNC has

been pulled low, the switches are automatically updated with

the new configuration and the Input Shift Register is disabled.

The ADG725 CSA and CSB data bits allow the user the flex-

ibility to change the configuration of either or both banks of the

multiplexer.

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the ADG725/ADG731 is via a serial

bus that uses standard protocol compatible with microcontrollers

and DSP processors. The communications channel is a 3-wire

interface consisting of a clock signal, a data signal, and a

synchronization signal. The ADG725/ADG731 requires an

8-bit data-word with data valid on the falling edge of SCLK.

Figures 4–7 illustrate simple 3-wire interfaces with popular

microcontrollers and DSPs.

ADSP-21xx to ADG725/ADG731 Interface

The ADSP-21xx family of DSPs are easily interfaced to the

ADG725/ADG731 without the need for extra logic. Figure 4

shows an example of an SPI interface between the ADG725/

ADG731 and the ADSP-2191M. SCK of the ADSP-2191M

drives the SCLK of the mux, while the MOSI output drives the

serial data line, DIN. SYNC is driven from one of the port lines,

in this case SPIxSEL.

SPIxSEL

ADSP-2191M*

MOSI

SYNC

ADG725/ADG731

DIN

SCK

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 4. ADSP-2191M to ADG725/ADG731 Interface

REV. A

–13–

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