AD9245(RevE) Просмотр технического описания (PDF) - Analog Devices

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AD9245
(Rev.:RevE)

14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter

Analog Devices 

Data Sheet

The SHA can be driven from a source that keeps the signal

peaks within the allowable range for the selected reference

voltage. The minimum and maximum common-mode input

levels are defined as

VCM MIN

=

VREF

2

VCM MAX

=

(AVDD + VREF )

2

The minimum common-mode input level allows the AD9245 to

accommodate ground referenced inputs.

Although optimum performance is achieved with a differential

input, a single-ended source can be applied to VIN+ or VIN–.

In this configuration, one input accepts the signal, while the

opposite input is set to midscale by connecting it to an

appropriate reference. For example, a 2 V p-p signal can be

applied to VIN+ while a 1 V reference is applied to VIN–. The

AD9245 then accepts an input signal varying between 2 V and

0 V. In the single-ended configuration, distortion performance

can degrade significantly as compared to the differential case.

However, the effect is less noticeable at lower input frequencies.

Differential Input Configurations

As previously detailed, optimum performance is achieved while

driving the AD9245 in a differential input configuration. For

baseband applications, the AD8351 differential driver provides

excellent performance and a flexible interface to the ADC. The

output common-mode voltage of the AD8351 is easily set to

AVDD/2, and the driver can be configured in a Sallen-Key filter

topology to provide band limiting of the input signal.

2V p-p

0.1µF

1.2kΩ

1kΩ

33Ω

50Ω

25Ω AD8351

25Ω 0.1mF

1kΩ

20pF

33Ω

AVDD

VIN+

AD9245

VIN–

AGND

Figure 40. Differential Input Configuration Using the AD8351

At input frequencies in the second Nyquist zone and above, the

performance of most amplifiers is not adequate to achieve the

true performance of the AD9245. This is especially true in IF

undersampling applications where frequencies in the 70 MHz to

100 MHz range are being sampled. For these applications,

differential transformer coupling is the recommended input

configuration. The value of the shunt capacitor is dependent on

the input frequency and source impedance and should be

reduced or removed. An example is shown in Figure 41.

AD9245

2V p-p

49.9Ω

0.1µF

33Ω

20pF

33Ω

1kΩ

1kΩ

AVDD

VIN+

AD9245

VIN–

AGND

Figure 41. Differential Transformer-Coupled Configuration

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few MHz, and excessive signal power can also cause

core saturation, which leads to distortion.

Single-Ended Input Configuration

A single-ended input can provide adequate performance in

cost-sensitive applications. In this configuration, there is a

degradation in SFDR and distortion performance due to the

large input common-mode swing (see Figure 13). However, if

the source impedances on each input are matched, there should

be little effect on SNR performance. Figure 42 details a typical

single-ended input configuration.

2V p-p

1kΩ

49.9Ω

0.33µF 1kΩ

+

10µF

1kΩ

0.1µF

1kΩ

33Ω

20pF

33Ω

AVDD

VIN+

AD9245

VIN–

AGND

Figure 42. Single-Ended Input Configuration

CLOCK INPUT CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals, and as a result can be sensitive

to clock duty cycle. Commonly a 5% tolerance is required on the

clock duty cycle to maintain dynamic performance characteristics.

The AD9245-80 and AD9245-65 contain a clock duty cycle

stabilizer (DCS) that retimes the nonsampling edge, providing an

internal clock signal with a nominal 50% duty cycle. This allows a

wide range of clock input duty cycles without affecting the

performance of the AD9245. As shown in Figure 21, noise and

distortion performance is nearly flat for a 30% to 70% duty cycle

with the DCS on.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately 100 clock cycles to

allow the DLL to acquire and lock to the new rate.

Rev. E | Page 19 of 32

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