AD9216-105PCB Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
Список матч
AD9216-105PCB Datasheet PDF : 20 Pages
| |||
Preliminary Technical Data
AD9216
AD9216–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Test
AD9216BCP-65/80
AD9216BCP-105
Parameter
Temp Level Min Typ
Max Min Typ Max Unit
RESOLUTION
Full VI
ACCURACY
No Missing Codes Guaranteed
Full VI
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Full VI
Full IV
Full V
Integral Nonlinearity (INL)2
25°C I
Full V
25°C I
TEMPERATURE DRIFT
Offset Error
Gain Error1
Full V
Full V
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full VI
Load Regulation @ 1.0 mA
Full V
Output Voltage Error (0.5 V Mode) Full V
Load Regulation @ 0.5 mA
Full V
INPUT REFERRED NOISE
Input Span = 1 V
25°C V
Input Span = 2.0 V
25°C V
ANALOG INPUT
Input Span = 1.0 V
Full IV
Input Span = 2.0 V
Input Capacitance3
Full IV
Full V
REFERENCE INPUT RESISTANCE Full V
POWER SUPPLIES
Supply Voltages
AVDD
Full IV
DRVDD
Full IV
Supply Current
IAVDD2
IDRVDD2
Full V
Full V
PSRR
Full V
POWER CONSUMPTION
DC Input4
Sine Wave Input2
Standby Power5
Full V
Full VI
Full V
MATCHING CHARACTERISTICS
Offset Error
Full V
Gain Error
Full V
10
10
±0.3
±1.0
±0.5
±0.5
±0.5
±0.5
±15
±30
±5
0.8
±2.5
0.1
0.8
0.4
1
2
2
7
10
Bits
10
±TBD
±TBD
±TBD
±TBD
±0.30
±1.0
±0.5
±0.5
±0.5
±0.5
±TBD
±TBD
±TBD
±TBD
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
±15
ppm/°C
±30
ppm/°C
±35
±5
±35 mV
0.8
mV
±2.5
mV
0.1
mV
0.8
LSB rms
0.4
LSB rms
1
V p-p
2
V p-p
2
pF
7
k?
2.7 3.0
3.3
2.25 2.5
3.6
TBD/TBD
TBD/TBD
±0.01
TBD/TBD
215/238
1/1
±0.1
±0.05
2.7 3.0 3.3
2.25 2.5 3.6
TBD
TBD
±0.01
TBD
280
1
±0.1
±0.05
V
V
mA
mA
% FSR
mW
mW
mW
% FSR
% FSR
1 Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference).
2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure xx for the equivalent analog input
structure.
4 Measured with dc input at maximum clock rate.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.
Rev. PrD
Page 3 of 20
6/15/2004
Share Link: 