datasheetbank_Logo
Технический паспорт Поисковая и бесплатно техническое описание Скачать

AD7783 Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге
Компоненты Описание
Список матч
AD7783 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD7783
TIMING CHARACTERISTICS1, 2 (VDD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz;
Input Logic 0 = 0 V, Logic 1 = VDD, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
(B Version)
Unit
Conditions/Comments
t1
tADC
t2
t3
t43
t75
t8
t9
Slave Mode Timing
t5
t6
Master Mode Timing
t5
t6
t10
30.5176
50.54
0
60
80
2 ¥ tADC
0
60
80
10
80
0
10
80
100
100
t1/2
t1/2
t1/2
3t1/2
ms typ
ms typ
ns min
ns max
ns max
ns typ
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns min
ms typ
ms typ
ms min
ms max
Crystal Oscillator Period
19.79 Hz Update Rate
CS Falling Edge to DOUT Active
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
Channel Settling Time
SCLK Active Edge to Data Valid Delay4
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
Bus Relinquish Time after CS Inactive Edge
CS Rising Edge to SCLK Inactive Edge Hold Time
SCLK Inactive to DOUT High
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK Low Pulse Width
DOUT Low to First SCLK Active Edge4
NOTES
1Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2See Figure 2.
3These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.
4SCLK active edge is falling edge of SCLK.
5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin-
quish times of the part and as such are independent of external bus loading capacitances.
TO OUTPUT
PIN
50pF
ISINK (1.6mA WITH VDD = 5V
100A WITH VDD = 3V)
1.6V
ISOURCE( 200A WITH VDD = 5V
100A WITH VDD = 3V)
Figure 1. Load Circuit for Timing Characterization
–4–
REV. C

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]