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AD7781CRZ-REEL

20-Bit, Pin-Programmable, Low Power Sigma-Delta ADC

Analog Devices 

AD7781

APPLICATIONS INFORMATION

The AD7781 provides a low cost, high resolution analog-to-

digital function. Because the analog-to-digital function is

provided by a Σ-Δ architecture, the part is more immune to

noisy environments, making it ideal for use in sensor measure-

ment and industrial and process control applications.

WEIGH SCALES

Figure 23 shows the AD7781 being used in a weigh scale

application. The load cell is arranged in a bridge network and

gives a differential output voltage between its OUT+ and OUT−

terminals. Assuming a 5 V excitation voltage, the full-scale

output range from the transducer is 10 mV when the sensitivity

is 2 mV/V. The excitation voltage for the bridge can be used to

directly provide the reference for the ADC because the refer-

ence input range includes the supply voltage.

A second advantage of using the AD7781 in transducer-based

applications is that the bridge power-down switch (BPDSW)

can be fully utilized in low power applications. The bridge power-

down switch is connected in series with the low side of the bridge.

In normal operation, the switch is closed and measurements

can be taken. In applications where power is of concern, the

AD7781 can be placed in power-down mode, significantly

reducing the power consumed in the application. In addition,

the bridge power-down switch is opened while in power-down

mode, thus avoiding unnecessary power consumption by the

front-end transducer. When the part is taken out of power-down

mode and the bridge power-down switch is closed, the user should

ensure that the front-end circuitry is fully settled before attempting

to read from the AD7781.

The load cell has an offset, or tare, associated with it. This tare is

the main component of the system offset (load cell + ADC) and

is similar in magnitude to the full-scale signal from the load cell.

For this reason, calibrating the offset and gain of the AD7781

alone is not sufficient for optimum accuracy; a system calibration

that calibrates the offset and gain of the ADC, plus the load cell,

is required. A microprocessor can be used to perform the calibra-

tions. The offset error (the conversion result from the AD7781

when no load is applied to the load cell) and the full-scale error

(the conversion result from the ADC when the maximum load

is applied to the load cell) must be determined. Subsequent

conversions from the AD7781 are then corrected, using the

offset and gain coefficients that were calculated from these

calibrations.

AD7781 PERFORMANCE IN A WEIGH SCALE SYSTEM

If the load cell has a sensitivity of 2 mV/V and a 5 V excitation

voltage is used, the full-scale signal from the load cell is 10 mV.

When the AD7781 (C grade) operates with a 10 Hz output data

rate and the gain is set to 128, the device has a p-p resolution of

18.2 bits when the reference is equal to 5 V. Postprocessing the

data from the AD7781 using a microprocessor increases the p-p

resolution. For example, an average by 4 in the microprocessor

increases the accuracy by 2 bits. The noise-free counts value is

equal to

Noise-Free Counts = (2Effective ) Bits × (FSLC/FSADC)

where:

Effective Bits = 18.2 bits (AD7781) + 2 bits (due to postprocessing

in the microprocessor).

FSLC is the full-scale signal from the load cell (10 mV).

FSADC is the full-scale input range when gain = 128 and

VREF = 5 V (78 mV).

The noise-free counts is equal to

(218.2 + 2) × (10 mV/78 mV) = 154,422

This example shows that with a 5 V supply, 154,422 noise-free

counts can be achieved with the AD7781.

EMI RECOMMENDATIONS

For simplicity, the EMI filters are not included in Figure 23.

However, an R-C antialiasing filter should be included on each

analog input. This filter is needed because the on-chip digital

filter does not provide any rejection around the master clock or

multiples of the master clock. Suitable values are a 1 kΩ resistor

in series with each analog input, a 0.1 μF capacitor from AIN(+)

to AIN(−), and 0.01 μF capacitors from AIN(+)/AIN(−) to GND.

VDD

IN+

OUT–

IN–

REFIN(+)

OUT+ AIN(+)

AIN(–)

GND

AVDD

G=1

OR 128

20-BIT Σ-Δ

ADC

REFIN(–)

BPDSW

INTERNAL

CLOCK

AD7781

Figure 23. Weigh Scales Using the AD7781

DOUT/RDY

SCLK

DVDD

FILTER

PDRST

GAIN

Rev. 0 | Page 14 of 16

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