AD7780 Просмотр технического описания (PDF) - Analog Devices
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AD7780 Datasheet PDF : 16 Pages
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AD7780
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SCLK 1
14 FILTER
DOUT/RDY 2
13 PDRST
NC 3 AD7780 12 DVDD
GAIN 4 TOP VIEW 11 AVDD
(Not to Scale)
AIN(+) 5
10 GND
AIN(–) 6
9 BPDSW
REFIN(+) 7
8 REFIN(–)
NC = NO CONNECT
Figure 6. SOIC Pin Configuration
NC 1
16 NC
SCLK 2
15 FILTER
DOUT/RDY 3
NC 4
GAIN 5
AIN(+) 6
AD7780
TOP VIEW
(Not to Scale)
14 PDRST
13 DVDD
12 AVDD
11 GND
AIN(–) 7
10 BPDSW
REFIN(+) 8
9 REFIN(–)
NC = NO CONNECT
Figure 7. TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
SOIC TSSOP Mnemonic Description
1
2
SCLK
Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK pin has a Schmitt-
triggered input. The serial clock can be active only when transferring data from the AD7780. The data
from the AD7780 can be read as a continuous 32-bit word. Alternatively, SCLK can be noncontinuous
during the data transfer, with the information being transmitted from the ADC in smaller data batches.
2
3
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose: as a data ready pin, going low to
indicate the completion of a conversion, and as a serial data output pin to access the data register of the
ADC. Eight status bits accompany each data read (see Figure 22). The DOUT/RDY falling edge can be used
as an interrupt to a processor, indicating that new data is available. If the data is not read after the conver-
sion, the pin goes high before the next update occurs. The serial interface is reset each time that a conversion is
available. Therefore, the user must ensure that any conversions being transmitted are completed before
the next conversion is available.
3
1, 4, 16 NC
No Connect. This pin can be left floating.
4
5
GAIN
Gain Select Pin. When GAIN is low, the gain is set to 128. When GAIN is high, the gain is set to 1.
5
6
AIN(+)
Analog Input. AIN(+) is the positive terminal of the differential analog input pair, AIN(+)/AIN(−).
6
7
AIN(−)
Analog Input. AIN(−) is the negative terminal of the differential analog input pair, AIN(+)/AIN(−).
7
8
8
9
REFIN(+)
REFIN(−)
Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). The nomi-
nal reference voltage (REFIN(+) − REFIN(−)) is 5 V, but the part can function with a reference of 0.5 V to AVDD.
Negative Reference Input.
9
10
BPDSW
Bridge Power-Down Switch to GND. When PDRST is high, the bridge power-down switch is closed. When
PDRST is low, the switch is opened.
10 11
GND
Ground Reference Point.
11 12
12 13
13 14
AVDD
DVDD
PDRST
Supply Voltage, 2.7 V to 5.25 V.
Digital Interface Supply Voltage. The logic levels for the serial interface pins and the digital control pins
are related to this supply, which is between 2.7 V and 5.25 V. The DVDD voltage is independent of the
voltage on AVDD; therefore, AVDD can equal 5 V with DVDD at 3 V or vice versa.
Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode, and the low-side power
switch is opened. All the logic on the chip is reset, and the DOUT/RDY pin is tristated. When PDRST is high,
the ADC is taken out of power-down mode. The on-chip clock powers up and settles, and the ADC
continuously converts. In addition, the low-side power switch is closed. The internal clock requires
approximately 1 ms to power up.
14 15
FILTER
Filter Select. When FILTER is low, the fast settling filter is selected. The update rate is set to 16.7 Hz, which
gives a filter settling time of 120 ms. When FILTER is high, the high rejection filter is selected. The update
rate is set to 10 Hz, which gives a filter settling time of 300 ms. With this filter, the stop-band (higher than
fADC) attenuation is better than −45 dB.
Rev. A | Page 7 of 16
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