AD7482BSTZ Просмотр технического описания (PDF) - Analog Devices
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AD7482BSTZ Datasheet PDF : 20 Pages
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111...111
111...110
111...000
011...111
1LSB = VREF/4096
000...010
000...001
000...000
0V
0.5LSB
–OFFSET
+VREF – 1.5LSB
–OFFSET
ANALOG INPUT
Figure 22. Transfer Characteristic with Negative Offset
Table 5 shows the expected ADC result for a given analog input
voltage with different offset values and with CLIP tied to logic high.
The combined advantages of the offset and overrange features of
the AD7482 are shown in Table 6. Table 6 shows the same range of
analog input and offset values as Table 5 but with the clipping
feature disabled.
Table 5. Clipping Enabled (CLIP = 1)
−128 0
+256
Offset VIN
ADC DATA, D[0:11]
D12
−200 mV
0
0
0
111
−156.25 mV
0
0
0
110
0V
0
0
256
100
+78.125 mV
0
128
384
000
+2.3431 V
3711
3839
4095
000
+2.5 V
3967
4095
4095
001
+2.5775 V
4095
4095
4095
011
+2.7 V
4095
4095
4095
111
Table 6. Clipping Disabled (CLIP = 0)
−128
0
+256
Offset VIN
ADC DATA, D[0:12]
−200 mV
−156.25 mV
0V
−456
−328
−72
−384
−256
0
−128
0
256
+78.125 mV
+2.3431 V
+2.5 V
+2.5775 V
+2.7 V
0
3711
3967
4095
4296
128
3839
4095
4223
4424
384
4095
4351
4479
4680
If the CLIP input is at logic low, the overrange indicator is disabled
and the AD7482 is able to achieve output codes outside the
nominal 12-bit range of 0 to 4095 (see Figure 6). D12 acts as an
indicator that the ADC is outside this nominal range. If the ADC is
outside this nominal range on the negative side, the ADC outputs a
twos complement code and if the ADC is outside the range on the
positive side, the ADC outputs a straight binary code as normal.
If D12 is Logic 1, D11 indicates if the ADC is out of range on
the positive or negative side. If D11 is Logic 1, the ADC is outside
the nominal range on the negative side and the output code is a
13-bit twos complement number (a negative number). If D11 is
AD7482
Logic 0, the ADC is outside the nominal range on the positive side
and the output code is a 13-bit straight binary code, see Table 7.
Table 7. DB14, DB13 Decoding, CLIP = 0
DB12 DB11 Output Coding
0
0
Straight binary – inside nominal range
0
1
Straight binary – inside nominal range
1
0
Straight binary – outside nominal range
1
1
Twos complement – outside nominal range
Values from −327 to +327 can be written to the offset register.
These values correspond to an offset of ±200 mV. A write to the
offset register is performed by writing a 13-bit word to the part
as detailed in the Parallel Interface section. The 10 LSBs of the
13-bit word contain the offset value, whereas the 3 MSBs must
be set to 0. Failure to write 0s to the 3 MSBs may result in the
incorrect operation of the device.
PARALLEL INTERFACE
The AD7482 features two parallel interfacing modes. These
modes are selected by the mode pins (see Table 8).
Table 8. Operating Modes
Operating Mode
Do Not Use
Parallel Mode 1
Parallel Mode 2
Do Not Use
Mode 2
0
0
1
1
Mode 1
0
1
0
1
In Parallel Mode 1, the data in the output register is updated on
the rising edge of BUSY at the end of a conversion and is available
for reading almost immediately afterward. Using this mode,
throughput rates of up to 2.5 MSPS can be achieved. This mode
is to be used if the conversion data is required immediately after
the conversion is completed. An example where this may be of use
is if the AD7482 is operating at much lower throughput rates in
conjunction with the nap mode (for power saving reasons), and
the input signal is being compared with set limits within the DSP or
other controller. If the limits are exceeded, the ADC is brought
immediately into full power operation and commences sampling at
full speed. Figure 31 shows a timing diagram for the AD7482
operating in Parallel Mode 1 with both CS and RD tied low.
In Parallel Mode 2, the data in the output register is not updated
until the next falling edge of CONVST. This mode can be used
where a single sample delay is not vital to the system operation,
and conversion speeds of greater than 2.5 MSPS are desired. For
example, this may occur in a system where a large amount of
samples are taken at high speed before an FFT is performed for
frequency analysis of the input signal. Figure 32 shows a timing
diagram for the AD7482 operating in Parallel Mode 2 with both
CS and RD tied low.
Rev. B | Page 15 of 20
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