AD73460 Просмотр технического описания (PDF) - Analog Devices
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AD73460 Datasheet PDF : 32 Pages
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AD73460
words to the AFE. In certain configurations, data can be written
to the device to coincide with the output sample being shifted
out of the serial register—see section on interfacing devices. The
serial clock rate (CRB:2–3) defines how many 16-bit words
can be written to a device before the next output sample event
will happen.
The SPORT2 block diagram, shown in Figure 7, details the
blocks associated with AFE including the eight control registers
(A–H), external AMCLK to internal DMCLK divider and serial
clock divider. The divider rates are controlled by the setting of
Control Register B. The AFE features a master clock divider
that allows users the flexibility of dividing externally available
high frequency DSP clocks to generate a lower frequency master
clock internally in the AFE, which may be more suitable for
either serial transfer or sampling rate requirements. The master
clock divider has five divider options (÷ 1 default condition, ÷ 2,
÷ 3, ÷ 4, ÷ 5) that are set by loading the master clock divider field
in Register B with the appropriate code (see Table VIII). Once
the internal device master clock (DMCLK) has been set using
the master clock divider, the sample rate and serial clock set-
tings are derived from DMCLK.
Master Clock Divider
The AFE features a programmable master clock divider that
allows the user to reduce an externally available master clock, at
pin AMCLK, by one of the ratios 1, 2, 3, 4, or 5 to produce an
internal master clock signal (DMCLK) that is used to calculate
the sampling and serial clock rates. The master clock divider is
programmable by setting CRB:4–6. Table III shows the division
ratio corresponding to the various bit settings. The default divider
ratio is divide-by-one.
Table III. DMCLK (Internal) Rate Divider Settings
MCD2
0
0
0
0
1
1
1
1
MCD1
0
0
1
1
0
0
1
1
MCD0
0
1
0
1
0
1
0
1
DMCLK Rate
AMCLK
AMCLK/2
AMCLK/3
AMCLK/4
AMCLK/5
AMCLK
AMCLK
AMCLK
AMCLK
(EXTERNAL)
MCLK
DIVIDER
DMCLK
(INTERNAL)
SE
ARESET
SERIAL PORT
(SPORT)
SDIFS
SDI
SERIAL REGISTER
3
SCLK
DIVIDER
2
SCLK2
SDOFS
SDO
8
8
8
8
8
CONTROL
REGISTER
A
CONTROL
REGISTER
B
CONTROL
REGISTER
C
CONTROL
REGISTER
D
CONTROL
REGISTER
E
8
CONTROL
REGISTER
CONTROL
REGISTER
CONTROL
REGISTER
F
G
H
Figure 7. SPORT Block Diagram
SPORT2 can work at four different serial clock (SCLK) rates:
chosen from DMCLK, DMCLK/2, DMCLK/4, or DMCLK/8,
where DMCLK is the internal or device master clock resulting
from the external or pin master clock being divided by the mas-
ter clock divider. Care should be taken when selecting Master
Clock, Serial Clock, and Sample Rate divider settings to ensure
that there is sufficient time to read all the data from the AFE
before the next sample interval.
SPORT Register Maps
There are eight control registers for the AFE, each eight bits
wide. Table VI shows the control register map for the AFE.
The first two control registers, CRA and CRB, are reserved for
controlling SPORT2. They hold settings for parameters such as
bit rate, internal master clock rate, and device count. If multiple
AFEs are cascaded, registers CRA and CRB on both devices
must be programmed with the same setting to ensure correct
operation. The other six registers, CRC through CRH, are used
to hold control settings for the Reference, Power Control, ADC
channel, and PGA sections of the device. It is not necessary that
the contents of CRC through CRH on each AFE are similar.
Control registers are written to on the negative edge of SCLK2.
Serial Clock Rate Divider
The AFE features a programmable serial clock divider that allows
users to match the serial clock (SCLK2) rate of the data to that
of the DSP. The maximum SCLK2 rate available is DMCLK
and the other available rates are: DMCLK/2, DMCLK/4 and
DMCLK/8. The slowest rate (DMCLK/8) is the default SCLK2
rate. The serial clock divider is programmable by setting bits
CRB:2–3. Table IV shows the serial clock rate corresponding to
the various bit settings.
Table IV. SCLK Rate Divider Settings
SCD1
0
0
1
1
SCD0
0
1
0
1
SCLK2 Rate
DMCLK/8
DMCLK/4
DMCLK/2
DMCLK
Decimation Rate Divider
The AFE features a programmable decimation rate divider that
allows users flexibility in matching the AFE’s ADC sample rates
to the needs of the DSP software. The maximum sample rate
available is DMCLK/256, and the other available rates are
DMCLK/512, DMCLK/1024, and DMCLK/2048. The slowest
rate (DMCLK/2048) is the default sample rate. The sample rate
divider is programmable by setting bits CRB:0–1. Table V shows
the sample rate corresponding to the various bit settings.
Table V. Decimation Rate Divider Settings
DR1
0
0
1
1
DR0
0
1
0
1
Sample Rate
DMCLK/2048
DMCLK/1024
DMCLK/512
DMCLK/256
–14–
REV. A
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