AD73460(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD73460 Datasheet PDF : 32 Pages
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AD73460
CONTROL REGISTER H
Table XV. Control Register H Description
7
INV
6
TME
5
CH6
4
CH5
3
CH4
2
CH3
1
CH2
0
CH1
Bit Name
0
CH1
1
CH2
2
CH3
3
CH4
4
CH5
5
CH6
6
TME
7
INV
Description
Channel 1 Select
Channel 2 Select
Channel 3 Select
Channel 4 Select
Channel 5 Select
Channel 6 Select
Test Mode Enable
Enable Invert Channel Mode
OPERATION
Resetting the AFE
The ARESET pin resets all the control registers. All the AFE
registers are reset to zero, indicating that the default SCLK2
rate (DMCLK/8) and sample rate (DMCLK/2048) are at a mini-
mum. As well as resetting the control registers of the AFE using
the ARESET pin, the device can be reset using the RESET bit
(CRA:7) in Control Register A. Both hardware and software
resets require four DMCLK cycles. On reset, DATA/PGM
(CRA:0) is set to 0 (default condition) thus enabling Control
Mode. The reset conditions ensure that the device must be
programmed to the correct settings after power-up or reset.
Following a reset, the SDOFS will be asserted approximately
2070 master (AMCLK) cycles after ARESET goes high. The
data that is output following the reset and during Control Mode
is random and contains no valid information until either data or
mixed mode is set.
Power Management
The individual functional blocks of the AFE can be enabled
separately by programming the power control register CRC.
(The Power Management functions of the DSP section are
separate and will be referred to later.) It allows certain sections
to be powered down if not required, which adds to the device’s
flexibility in that the user need not incur the penalty of having to
provide power for a certain section if it is not necessary to their
design. The power control registers provide individual control
settings for the major functional blocks on each analog front end
unit and also a global override that allows all sections to be
powered up/down by setting/clearing the bit. Using this method
the user could, for example, individually enable a certain section,
such as the reference (CRC:5), and disable all others. The glo-
bal power-up (CRC:0) can be used to enable all sections, but if
power-down is required using the global control, the reference
will still be enabled; in this case, because its individual bit is set.
Refer to Table X for details of the settings of CRC. CRD–CRF
can be used to control the power status of individual channels
allowing multiple channels to be powered down if required.
Operating Modes
Three operating modes are available on the AFE. They are
Control (Program) Mode, Data Mode, and Mixed Control/
Data Mode. The device configuration—register settings—can be
changed only in Program and Mixed Program/Data Modes. In
all modes, transfers of information to or from the device occur
in 16-bit packets, therefore the DSP engine’s SPORT will be
programmed for 16-bit transfers.
Control Mode
In Control Mode, CRA:0 = 0, the user writes to the control
registers to set up the device for desired operation—SPORT2
operation, cascade length, power management, input/output gain,
etc. In this mode, the 16-bit information packet sent to the device
by the DSP is interpreted as a control word whose format is shown
in Table VII. In this mode, the user m=ust address the device to
be programmed using the address field of the control word. This
field is read by the device and if it is zero (000 bin), the device
recognizes the word as being addressed to it. If the address field is
not zero, it is then decremented and the control word is passed
out of the device—either to the next device in a cascade or back to
the DSP. This 3-bit address format allows the user to uniquely
address any device in a cascade. If the AFE is used in a standalone
configuration connected to the DSP, the device address corre-
sponds to 0.
Following reset, when the SE pin is enabled, the AFE responds
by raising the SDOFS pin to indicate that an output sample
event has occurred. Control words can be written to the device
to coincide with the data being sent out of SPORT2, as shown in
Figure 9 (Directly Coupled), or they can lag the output words
by a time interval that should not exceed the sample interval
(Indirectly Coupled). Refer to the Digital Interface section for
more information. After reset, output frame sync pulses will
occur at a slower default sample rate, which is DMCLK/2048,
until Control Register B is programmed, after which the SDOFS
will be pulsed at the selected rate. While the AFE is in Control
Mode, the data output by the device is random and should not
be interpreted as ADC data.
–18–
REV. 0
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