AD73460
CONTROL REGISTER B
CONTROL REGISTER C
CONTROL REGISTER D
Table IX. Control Register B Description
7
CEE
6
5
4
3
2
MCD2 MCD1 MCD0 SCD1 SCD0
1
DR1
0
DR0
Bit Name
0
DR0
1
DR1
2
SCD0
3
SCD1
4
MCD0
5
MCD1
6
MCD2
7
CEE
Description
Decimation Rate (Bit 0)
Decimation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = OFF; 1 = Enabled)
Table X. Control Register C Description
7
RES
6
5
4
RU PUREF RES
3
RES
2
RES
1
RES
0
GPU
Bit Name
0
GPU
1
Reserved
2
Reserved
3
Reserved
4
Reserved
5
PUREF
6
RU
7
Reserved
Description
Global Power-Up Device (0 = Power Down; 1 = Power Up)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
REF Power (0 = Power Down; 1 = Power Up)
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
Must Be Programmed to Zero (0)
Table XI. Control Register D Description
7
6
5
4
3
2
1
0
PUI2 I2GS2 I2GS1 I2GS0 PUI1 I1GS2 I1GS1 I1GS0
Bit Name
0
I1GS0
1
I1GS1
2
I1GS2
3
PUI1
4
I2GS0
5
I2GS1
6
I2GS2
7
PUI2
Description
ADC1: Input Gain Select (Bit 0)
ADC1: Input Gain Select (Bit 1)
ADC1: Input Gain Select (Bit 2)
Power Control (ADC1): 1 = ON, 0 = OFF
ADC2: Input Gain Select (Bit 0)
ADC2: Input Gain Select (Bit 1)
ADC2: Input Gain Select (Bit 2)
Power Control (ADC2): 1 = ON, 0 = OFF
–16–
REV. 0