AD73322 Просмотр технического описания (PDF) - Analog Devices
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AD73322 Datasheet PDF : 43 Pages
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AD73322
TIMING CHARACTERISTICS (AVDD = +5 V ؎ 10%; DVDD = +5 V ؎ 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless
otherwise noted)
Parameter
Limit at
TA = –40؇C to +85؇C
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
61
24.4
24.4
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
Specifications subject to change without notice.
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
t1
t2
100A IOL
TO OUTPUT
PIN
CL
15pF
+2.1V
t3
Figure 1. MCLK Timing
100A IOH
Figure 2. Load Circuit for Timing Specifications
t1
t2
t3
MCLK
SCLK*
t 13
t5
t6
t4
* SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing
SE (I)
THREE-
STATE
SCLK (O)
SDIFS (I)
SDI (I)
THREE-
t9
STATE
SDOFS (O)
THREE-
STATE
SDO (O)
t7
t8
D15
D14
t 10
t8
t7
D1
D0
t12
t 11
D15
D2
D1
D0
Figure 4. Serial Port (SPORT)
D15
D15
D14
REV. B
–9–
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