CDB4391 Просмотр технического описания (PDF) - Cirrus Logic

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CDB4391

24-Bit, 192 kHz Stereo DAC with Volume Control

Cirrus Logic 

CS4391

5. PIN DESCRIPTION - PCM DATA MODE

Reset

RST

1

20

Logic Voltage

VL

2

19

Serial Data

SDATA

3

18

Serial Clock

SCLK

4

17

Left/Right Clock

LRCK

5

16

Master Clock

MCLK

6

15

See Description

M3

7

14

See Description (SCL/CCLK) M2

8

13

See Description (SDA/CDIN) M1

9

12

See Description (AD0/CS) M0

10

11

AMUTEC

AOUTA-

AOUTA+

VA

AGND

AOUTB+

AOUTB-

BMUTEC

CMOUT

FILT+

Channel A Mute Control

Differential Output

Differential Output

Analog Power

Analog Ground

Differential Output

Differential Output

Channel B Mute Control

Common Mode Voltage

Positive Voltage Reference

Reset - RST

Pin 1, Input

Function:

Hardware Mode: The device enters a low power mode and the internal state machine is reset to the de-

fault setting when low. When high, the device becomes operational.

Control Port Mode: The device enters a low power mode and all internal registers are reset to the default

settings, including the control port, when low. When high, the control port becomes operational and the

PDN bit must be cleared before normal operation will occur. The control port can not be accessed when

reset is low. The Control Port Enable Bit must also be enabled after a device reset.

RST is required to remain low until the power supplies and clocks are applied and stable.

Interface Power - VL

Pin 2, Input

Function:

Digital interface power supply. Typically 1.8 to 5.0 VDC. The voltage on this pin determines the logic level

high threshold for the digital inputs. The voltage on VL is the maximum allowable input level for all digital

inputs.

Serial Audio Data - SDATA

Pin 3, Input

Function:

Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial

clock and the channel is determined by the Left/Right clock. The required relationship between the

Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or

the Mode Pins in Hardware Mode. The options are detailed in Figures 7-24.

DS335PP4

21

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