CDB4391 Просмотр технического описания (PDF) - Cirrus Logic

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CDB4391

24-Bit, 192 kHz Stereo DAC with Volume Control

Cirrus Logic 

CS4391

SWITCHING CHARACTERISTICS - SPI CONTROL PORT

(TA = 25° C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF)

Parameter

Symbol

Min

Max

SPI Mode

CCLK Clock Frequency

RST Rising Edge to CS Falling

CCLK Edge to CS Falling

CS High Time Between Transmissions

CS Falling to CCLK Edge

CCLK Low Time

CCLK High Time

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

fsclk

-

6

tsrs

500

-

(Note 24)

tspi

500

-

tcsh

1.0

-

tcss

20

-

tscl

66

-

tsch

66

-

tdsu

40

-

(Note 25)

tdh

15

-

(Note 26)

tr2

-

100

(Note 26)

tf2

-

100

Unit

MHz

ns

ns

µs

ns

ns

ns

ns

ns

ns

ns

Notes: 24. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

25. Data must be held for sufficient time to bridge the transition time of CCLK.

26. For FSCK < 1 MHz

RST

t srs

CS

t spi t css

t scl t sch

t csh

CCLK

t r2

t f2

C D IN

t dsu t dh

Figure 4. SPI Control Port Timing

DS335PP4

11

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