CDB4391 Просмотр технического описания (PDF) - Cirrus Logic

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CDB4391

24-Bit, 192 kHz Stereo DAC with Volume Control

Cirrus Logic 

CS4391

SWITCHING CHARACTERISTICS - I2C CONTROL PORT

(TA = 25° C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF)

Parameter

Symbol

Min

Max

I2C® Mode

SCL Clock Frequency

fscl

-

100

RST Rising Edge to Start

tirs

500

-

Bus Free Time Between Transmissions

tbuf

4.7

-

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

-

Clock Low time

tlow

4.7

-

Clock High Time

thigh

4.0

-

Setup Time for Repeated Start Condition

tsust

4.7

-

SDA Hold Time from SCL Falling

(Note 23)

thdd

0

-

SDA Setup time to SCL Rising

tsud

250

-

Rise Time of Both SDA and SCL Lines

tr

-

1

Fall Time of Both SDA and SCL Lines

tf

-

300

Setup Time for Stop Condition

tsusp

4.7

-

Notes: 23. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Unit

KHz

ns

µs

µs

µs

µs

µs

µs

ns

µs

ns

µs

RST

t irs

Stop

Start

SDA

t buf

t hdst

t high

SCL

t lo w t hdd

R e p e a te d

S ta rt

t hdst

tf

t sud

t sust

tr

Figure 3. I2C Control Port Timing

Stop

t susp

10

DS335PP4

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