NXP Semiconductors
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
VI
CP input
GND
VI
Dn, CE input
GND
VM
t su(H)
t h(H)
VM
t su(L)
t h(L)
001aac447
Fig 7.
VM = 1.5 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
Set-up and hold times data output (Dn) to clock (CP) and clock enable input (CE) to clock (CP)
VI
OE input
GND
3.5 V
Qn output
VOL
VOH
Qn output
GND
VM
tPZL
VM
tPZH
VM
tPLZ
VOL + 0.3 V
tPHZ
VOH − 0.3 V
001aac448
Fig 8.
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load
3-state output (Qn) enable and disable times
74ABT823_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 23 March 2010
© NXP B.V. 2010. All rights reserved.
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