CS4398 Просмотр технического описания (PDF) - Cirrus Logic
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CS4398 Datasheet PDF : 46 Pages
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CS4398
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF)
Parameter
Symbol
Min
CCLK Clock Frequency
fsclk
-
RST Rising Edge to CS Falling
tsrs
500
CCLK Edge to CS Falling
CS High Time Between Transmissions
(Note 11)
tspi
500
tcsh
1.0
CS Falling to CCLK Edge
tcss
20
CCLK Low Time
tscl
66
CCLK High Time
tsch
66
CDIN to CCLK Rising Setup Time
tdsu
40
CCLK Rising to DATA Hold Time
(Note 12)
tdh
15
Rise Time of CCLK and CDIN
(Note 13)
tr2
-
Fall Time of CCLK and CDIN
(Note 13)
tf2
-
Transition time from CCLK to CDOUT valid
(Note 14) tscdov
-
Time from CS rising to CDOUT high-Z
(Note 15) tcscdo
-
Max
Unit
6
MHz
-
ns
-
ns
-
µs
-
ns
-
ns
-
ns
-
ns
-
ns
100
ns
100
ns
40
ns
20
ns
11. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
12. Data must be held for sufficient time to bridge the transition time of CCLK.
13. For FSCK < 1 MHz.
14. CDOUT should not be sampled during this time period.
15. This time is by design and not tested.
RST
t srs
CS
CCLK
C D IN
t spi t css
t r2
t scl t sch
t f2
t csh
CDOUT
t dsu t dh
H i-Im p eda nc e
t scdov
t scdov
t cscdo
Figure 9. Control Port Timing - SPI Format (Read/Write)
16
DS568F1
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