CS4398 Просмотр технического описания (PDF) - Cirrus Logic

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CS4398

120 dB, 192 kHz Multi-Bit DAC with Volume Control

Cirrus Logic 

CS4398

Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-

imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer

to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.

Figure 12. Recommended Mute Circuitry

4.4 Oversampling Modes

The CS4398 operates in one of three oversampling modes based on the input sample rate. Single-Speed

mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode

supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode sup-

ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.

4.5 Master and Serial Clock Ratios

The required MCLK-to-LRCK ratio and suggested SCLK-to-LRCK ratio are outlined in Table 1. MCLK can

be at any phase in regards to LRCK and SCLK. SCLK, LRCK and SDATA must meet the phase and timing

relationships outlined in Section 2. Some common MCLK frequencies have been outlined in Table 2.

MCLK/LRCK

SCLK/LRCK

LRCK

Single-Speed

256, 384, 512, 768*, 1024*, 1152*

32, 48, 64, 96, 128

Fs

Double-Speed

128, 192, 256, 384, 512*

32, 48, 64

Fs

64

32 (16 bits only)

Fs

Quad-Speed

96

128, 256*

32, 48

Fs

32, 64

Fs

192

32, 48, 64, 96

Fs

*These modes are only available in Control Port mode by setting the appropriate MCLKDIV bit.

Table 1. Clock Ratios

DS568F1

21

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