RS5C321B Просмотр технического описания (PDF) - RICOH Co.,Ltd.

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RS5C321B

ULTRA-COMPACT SERIAL REAL-TIME CLOCK ICs WITH 32.768kHz

RICOH Co.,Ltd. 

RS5C321A/B

2. Registers

2.1 Control Register 1 (at Eh)

D3

D2

D1

D0

—

—

WTEN ADJ

0

0

XSTP

BSY

(For write operation)

(For read operation)

±30-second Adjustment Bit

ADJ

Description

0

Ordinary operation

1

Second digit adjustment

Clock/Counter Busy-state Indication Bit

BSY

Description

0

Ordinary operation

1

Second digit carry or adjustment

Clock Counter Enable/Disable Setting Bit

WTEN

Description

0

Disabling of 1-second digit carry for clock counter

1

Enabling of 1-second digit carry for clock counter

Oscillator Halt Sensing Bit

XSTP

0

Ordinary oscillation

1

Oscillator halt sensing

Description

2.1-1 (ADJ)

The following operations are performed by setting the ADJ bit to 1.

After this bit is set to 1, the BSY bit is set to 1 for the maximum duration of 122.1µs.

If the WTEN bit is 0, these adjustment operations are started after the WTEN bit is set to 1.

1) For second digits ranging from “00” to “29” seconds:

Time counters smaller than seconds are reset and second digits are set to “00”.

2) For second digits ranging from “30” to “59” seconds:

Time counters smaller than seconds are reset and second digits are set to “00”. Minute digits are incremented by 1.

8

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