RS5C321B Просмотр технического описания (PDF) - RICOH Co.,Ltd.
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RS5C321B Datasheet PDF : 33 Pages
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RS5C321A/B
FUNCTIONAL DESCRIPTIONS
1. Addressing
A3
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
1
9
1
A1
B1
C1
D1
E1
F1
Address
A2 A1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Registers
A0
Data *1
D3
D2
D1
D0
0 1-second counter
(BANK=0)
S8
S4
S2
S1
1 10-second counter
(BANK=0)
—*2
S40
S20
S10
0 1-minute counter
(BANK=0)
M8
M4
M2
M1
1 10-minute counter
(BANK=0)
—
M40
M20
M10
0 1-hour counter
(BANK=0)
H8
H4
H2
H1
1 10-hour counter
(BANK=0)
—
—
P/A, H20
H10
0 Day of the week counter
(BANK=0)
—
W4
W2
W1
1 Scratch register*8
(BANK=0, 1) Scratch*8 Scratch*8 Scratch*8 Scratch*8
0 1-day counter
(BANK=0)
D8
D4
D2
D1
1 10-day counter
(BANK=0)
—
—
D20
D10
1-month counter
0
32kHz clock pulse control register
(BANK=0)
(BANK=1)
MO8
—
MO4
—
MO2
—
MO1
CLEN*7
1 10-month counter
(BANK=0)
—
—
—
MO10
0 1-year counter
(BANK=0)
Y8
Y4
Y2
Y1
1 10-year counter
0 Control register 1
1 Control register 2
(BANK=0)
(BANK=0, 1)
(BANK=0, 1)
Y80
—
12/24
Y40
Y20
Y10
—
WTE*N6/XST*P4 ADJ/BSY *3
—
BANK *5 TEST *6
*1) All the listed data can be read and written.
*2) The “—” mark indicates data which can be read only and set to “0” when read.
*3) The ADJ/BSY bit of the control register is set to ADJ for write operation and BSY for read operation.
*4) The WTEN/XSTP bit of the control register is set to WTEN for write operation and XSTP for read operation.
*5) The clock/calendar counter and the 32kHz clock pulse control register can be selected when the BANK=0 and BANK=1 respectively. To designate
the BANK is unnecessary for scratch register and control register 1/2.
*6) The WTEN bit and TEST bit are set to “1” when CE is “L”.
*7) The CLEN bit is set to 0, when initial power-on or XSTP is set to 1.
*8) Data may be written and read into/from the Scratch register, which actually is not used.
7
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