CY7C1481V33-100AC Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1481V33-100AC

2M x 36/4M x 18/1M x 72 Flow-through SRAM

Cypress Semiconductor 

PRELIMINARY

CY7C1481V33

CY7C1483V33

CY7C1487V33

Logic Block Diagrams (continued)

CY7C1487V33 – 1M x72

CLK

ADV

ADSC

ADSP

A[19:0]

20

GW

BWE

BW h

BWg

BWf

BWe

BW d

BWc

BWb

BWa

CE1

CE2

CE3

MODE

(A[1;0]) 2

BURST Q0

CE COUNTER

CLR

Q1

Q

ADDRESS

18

CE

D

REGISTER

18

D DQh, DPh Q

BYTEWRITE

REGISTERS

D DQg, DPg Q

BYTEWRITE

REGISTERS

D DQf, DPf Q

BYTEWRITE

REGISTERS

D DQe, DPe Q

BYTEWRITE

REGISTERS

D DQd, DPd Q

BYTEWRITE

REGISTERS

D DQc, DPc Q

BYTEWRITE

REGISTERS

D DQb, DPb Q

BYTEWRITE

REGISTERS

D DQa, DPa Q

BYTEWRITE

REGISTERS

D ENABLE CE Q

REGISTER

20

1M X72

MEMORY

ARRAY

72

72

OE

ZZ

.

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby

Current

D ENABLE DELAY Q

REGISTER

SLEEP

CONTROL

INPUT

REGISTERS

CLK

DQa,b,c,d,e,f,g,h

DPa,b,c,d,e,f,g,h

CY7C1481V33-150 CY7C1481V33-133 CY7C1481V33-117 CY7C1481V33-100

CY7C1483V33-150 CY7C1483V33-133 CY7C1483V33-117 CY7C1483V33-100

CY7C1487V33-150 CY7C1487V33-133 CY7C1487V33-117 CY7C1487V33-100 Unit

5.5

6.5

7.5

8.5

ns

TBD

TBD

TBD

TBD

mA

TBD

TBD

TBD

TBD

mA

Document #: 38-05284 Rev. *A

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