CY7C1481V33-100AC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1481V33-100AC Datasheet PDF : 30 Pages
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PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Cycle Descriptions (continued)[1, 2, 3, 4]
Next Cycle
Add. Used ZZ CE3 CE2 CE1 ADSP ADSC
Suspend Read Current
0
X
X
X
1
1
Suspend Read Current
0
X
X
1
X
1
Suspend Read Current
0
X
X
1
X
1
Begin Write Current
0
X
X
X
1
1
Begin Write Current
0
X
X
1
X
1
Begin Write External
0
0
1
0
1
0
Continue Write Next
0
X
X
X
1
1
Continue Write Next
0
X
X
1
X
1
Suspend Write Current
0
X
X
X
1
1
Suspend Write Current
0
X
X
1
X
1
ZZ “sleep”
None
1
X
X
X
X
X
ADV OE
1
0
1
1
1
0
1
X
1
X
X
X
0
X
0
X
1
X
1
X
X
X
DQ
Write
DQ
Read
Hi-Z Read
DQ
Read
Hi-Z Write
Hi-Z Write
Hi-Z Write
Hi-Z Write
Hi-Z Write
Hi-Z Write
Hi-Z Write
Hi-Z X
Interleaved Burst Sequence
First
Address
A[1:0]
00
01
10
11
Second
Address
A[1:0]
01
00
11
10
Third
Address
A[1:0]
10
11
00
01
Linear Burst Sequence
First
Address
A[1:0]
00
01
10
11
Second
Address
A[1:0]
01
10
11
00
Third
Address
A[1:0]
10
11
00
01
Fourth
Address
A[1:0]
11
10
01
00
Fourth
Address
A[1:0]
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
Description
Snooze mode
standby current
Device operation to
ZZ
ZZ recovery time
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
Min.
2tCYC
Max.
TBD
2tCYC
Unit
mA
ns
ns
Document #: 38-05284 Rev. *A
Page 10 of 30
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