WED3DL644V8BC Просмотр технического описания (PDF) - White Electronic Designs Corporation

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WED3DL644V8BC

4Mx64 SDRAM

White Electronic Designs Corporation 

White Electronic Designs

WED3DL644V

FIG.2

Mode Register Definition

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

11 10 9 8 7

Reserved* WB Op Mode

6 54 3

CAS Latency BT

2 10

Burst Length

Mode Register(Mx)

*Should program

M11, M10 = “ 0, 0”

to ensure compatibility

with future devices.

M2 M1 M0

000

001

010

011

100

101

110

111

Burst Length

M3 = 0

1

2

4

8

Reserved

Reserved

Reserved

Full Page

M3 = 1

1

2

4

8

Reserved

Reserved

Reserved

Reserved

M3

0

1

M6 M5 M4

00 0

00 1

01 0

01 1

10 0

10 1

11 0

11 1

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Reserved

2

3

Reserved

Reserved

Reserved

Reserved

M8

M7

M6-M0

Operating Mode

0

0

Defined

Standard Operation

-

-

-

All other states reserved

M9

Write Burst Mode

0

Programmed Burst Length

1

Single Location Access

BURST DEFINITION

Burst

Length

2

4

8

Full

Page

(y)

Starting Column Order of Accesses Within a Burst

Address

Type = Sequential Type = Interleaved

A0

0

0-1

0-1

0

1-0

1-0

A1 A0

00

01

10

11

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

A2 A1 A0

0 00

0 01

0 10

0 11

1 00

1 01

1 10

1 11

n = A0 - A9/8/7

(location 0-y)

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

Cn, Cn+1, Cn+2

Cn+3, Cn+4...

...Cn-1,

Cn...

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

Not Supported

August 2005

Rev. 6

5

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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