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WED3DL644V8BC

4Mx64 SDRAM

White Electronic Designs Corporation 

White Electronic Designs

WED3DL644V

Symbol

Type

CK

Input

CKE

Input

CE#

Input

RAS#, CAS#

WE#

Input

BA0,BA1

Input

A0-11,

A10/AP

Input

DQ

DQML0 - (DQ0-7)

DQMH0 - (DQ8-15)

DQML1 - (DQ16-23)

DQMH1 - (DQ24-31)

DQML2 - (DQ31-39)

DQMH2 - (DQ40-47)

DQML3 - (DQ48-55)

DQMH3 - (DQ56-63)

VCC, VSS

Input/Output

Input

Supply

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Signal

Pulse

Level

Pulse

Pulse

Level

Level

Level

Polarity Function

Positive Edge

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the

clock.

Activates the CK signal when high and deactivates the CK signal when low. By

Active High deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the

Self Refresh mode.

Active Low

CE# disable or enable device operation by masking or enabling all inputs except CK,

CKE and DQM.

Active Low

When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the

operation to be executed by the SDRAM.

—

Selects which SDRAM bank is to be active.

During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when

sampled at the rising clock edge.

During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when

sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke

Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high,

—

autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10/AP is

low, autoprecharge is disabled.

During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1

to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged

regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define

which bank to precharge.

—

Data Input/Output are multiplexed on the same pins

Pulse

Mask

Active High

The Data Input/Output mask places the DQ buffers in a high impedance state when

sampled high. In Read mode, DQM has a latency of two clock cycles and controls

the output buffers like an output enable. In Write mode, DQM has a latency of zero

and operates as a word mask by allowing input data to be written if it is low but blocks

the Write operation if DQM is high. Each DQM pin controls the byte in parentheses

associated with it.

Power and ground.

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol Min Max Units

Power Supply Voltage

VCC/VCCQ -1.0

+4.6

V

Input Voltage

VIN

-1.0 +4.6

V

Output Voltage

VOUT

-1.0

+4.6

V

Operating Temperature

tOPR

-40

+85

°C

Storage Temperature

tSTG

-55 +125

°C

Power Dissipation

PD

—

3.0

W

Short Circuit Output Current

IOS

—

50

mA

Stress greater than those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions greater than those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

(Voltage Referenced to: Vss = 0V)

Parameter

Symbol Min Typ Max Unit

Supply Voltage

VCC/VCCQ 3.0 3.3 3.6

V

Input High Voltage

VIH 2.0 3.0 VCC +0.3 V

Input Low Voltage

VIL -0.3 —

0.8

V

Output High Voltage (IOH =-2mA) VOH 2.4 —

—

V

Output Low Voltage (IOL = 2mA)

VOL — —

0.4

V

Input Leakage Voltage

IIL

-5 —

5

µA

Output Leakage Voltage

IOL -5 —

5

µA

CAPACITANCE

(TA = 25°C, f= 1MHZ, VCC = 3.3V)

Parameter

Symbol Max

Unit

Input Capacitance

CIN

8

pF

Input/Output Capacitance (DQ)

COUT

5

pF

August 2005

Rev. 6

3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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