V826516G04SXTG-B0 Просмотр технического описания (PDF) - Mosel Vitelic, Corp
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V826516G04SXTG-B0 Datasheet PDF : 14 Pages
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MOSEL VITELIC
V826516G04S
DDR SDRAM IDD SPEC TABLE
Symbol
B1(DDR266@CL=2)
Typical
Worst
IDD0
800
880
IDD1
1000
1120
IDD2P
200
240
IDD2F
360
440
IDD2Q
280
320
IDD3P
240
280
IDD3N
400
480
IDD4R
1360
1600
IDD4W
1480
1720
IDD5
1480
1720
IDD6 Normal
16
16
Low power
8
8
IDD7A
2600
3000
B0(DDR266@CL=2.5) A1(DDR200@CL=2)
Typical
Worst Typical Worst
800
880
640
720
1000
1120
800
920
200
240
160
200
360
440
320
360
280
320
240
280
240
280
200
240
400
480
320
400
1360
1600
1120
1320
1480
1720
1200
1360
1480
1720
1200
1360
16
16
16
16
8
8
8
8
2600
3000
2120
2480
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
16
8
mA
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
V826516G04S Rev. 1.5 March 2002
9
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