V62C3802048L Просмотр технического описания (PDF) - Mosel Vitelic, Corp

Номер в каталоге

Компоненты Описание

Список матч

V62C3802048L

Ultra Low Power 256K x 8 CMOS SRAM

Mosel Vitelic, Corp 

V62C3802048L(L)

Read Cycle (3,9) (Vcc = 2.7 to3.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)

Parameter

Symbol -55

-70

-85

-100

Unit Note

Read Cycle Time

Min Max Min Max Min Max Min Max

tRC

55 - 70 - 85 - 100 -

ns

Address Access Time

tAA

- 55 - 70 - 85 - 100 ns

Chip Enable Access Time

tACE

- 55 - 70 - 85 - 100 ns

Output Enable Access Time

tOE

- 40 - 40 - 40 -

50

ns

Output Hold from Address Change

tOH

10 - 10 - 10 - 10

-

ns

Chip Enable to Output in Low-Z

tCLZ

10 - 10 - 10 - 10

-

ns

4,5

Chip Disable to Output in High-Z

tCHZ

- 25 - 30 - 35 -

40

ns

4,5

Output Enable to Output in Low-Z

tOLZ

5-5-

5

-

5

-

ns

4,5

Output Disable to Output in High-Z

tOHZ

- 20 - 25 - 30 -

35

ns

4,5

Power-Up Time

tPU

0-0-

0

-

0

-

ns

5

Power-Down Time

tPD

- 55 - 70 - 85 - 100 ns

5

Write Cycle (3,11) (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)

Parameter

Write Cycle Time

Chip Enable to Write End

Address Setup to Write End

Address Setup Time

Write Pulse Width

Write Recovering Time

Data Valid to Write End

Data Hold Time

Write Enable to Output in High-Z

Output Active from Write End

Symbol -55

-70

-85

-100

Min Max Min Max Min Max Min Max

tWC

55 - 70 - 85 - 100 -

tCW

40 - 60 - 70 - 80

-

tAW

40 - 60 - 70 - 80

-

tAS

0-0-

0

-

0

-

tWP

40 - 50 - 60 - 70

-

tWR

0-0-

0

-

0

-

tDW

25 - 30 - 35 - 40

-

tDH

0-0-

0

-

0

-

tWZ

- 25 - 30

- 35

-

40

tOW

5-5-

5

-

5

-

Unit Note

ns

ns

ns

ns

ns

ns

ns

ns

ns

4,5

ns

4,5

6

REV. 1.2 May 2001 V62C3802048L(L)

Share Link: