V62C3802048L Просмотр технического описания (PDF) - Mosel Vitelic, Corp

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V62C3802048L

Ultra Low Power 256K x 8 CMOS SRAM

Mosel Vitelic, Corp 

V62C3802048L(L)

Data Retention Characteristics (L Version Only)(1)

Parameter

VCC for Data Retention

Data Retention Current

Symbol

VDR

ICCDR

Test Condition

CE1 > VCC - 0.2V or

CE2 < + 0.2V

Chip Deselect to Data Retention Time

tCDR

VIN > VCC - 0.2V or

Operation Recovery Time(2)

tR

VIN < 0.2V

Min

1.0

-

0

tRC

Max

-

1

Unit

V

µA

-

ns

-

ns

Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C)

VCC

CE

Vcc_typ

tCDR

Data Retention Mode

VDR > 1.0V

VIH

VDR

Vcc_typ

tR

VIH

Notes

1. L-version includes this feature.

2. This Parameter is samples and not 100% tested.

3. For test conditions, see AC Test Condition, Figure A.

4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.

5. This parameter is guaranteed, but is not tested.

6. WE is HIGH for read cycle.

7. CE1 and OE are LOW and CE2 is HIGH for read cycle.

8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.

9. All read cycle timings are referenced from the last valid address to the first transtion address.

10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.

11. All write cycle timings are referenced from the last valid address to the first transition address.

10

REV. 1.2 May 2001 V62C3802048L(L)

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