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UAA2062

Analog cordless telephone IC

Philips Electronics 

Philips Semiconductors

Analog cordless telephone IC

Product specification

UAA2062

FUNCTIONAL DESCRIPTION

Power supply and power management

POWER SUPPLY VOLTAGE

The UAA2062 is used in a cordless telephone handset and

in a base unit. The handset unit is battery powered and can

operate on three NiCad cells. The minimum supply voltage

(VCC) is 3.0 V. However the low-battery detector, crystal

oscillator, clock divider and internal voltage regulator will

function with a supply voltage of 2.85 V.

POWER SAVING OPERATION MODES

When the UAA2062 is used in a handset, it is important to

reduce the current consumption. There are 3 power saving

modes in addition to the active mode:

1. In the active mode all blocks are powered.

2. In the RX mode, all circuitry in the receiver part is

powered.

3. In the standby mode, all circuitry is powered down

except the crystal oscillator, the microcontroller

interface and the Vref(PLL) block.

4. In the inactive mode, all circuitry is powered down

except the microcontroller interface and the Vref(PLL)

block.

Latch memory is maintained in all modes. Table 1 shows

which blocks are powered in each mode.

Table 1 Power saving operation modes

CIRCUIT BLOCK

Microcontroller interface

Vref(PLL)

Crystal oscillator

RF receiver and RX PLL

VB reference

Carrier and low-battery detectors

Data comparator

TX PLL and PA

RX and TX audio paths

ACTIVE

MODE

X

X

X

X

X

X

X

X

X

RX MODE

X

X

X

X

X

X

X

−

−

STANDBY

MODE

X

X(1)

X

−

−

−

−

−

−

INACTIVE

MODE

X

X(1)

−

−

−

−

−

−

−

Note

1. In the standby mode and in the inactive mode, by default, Vref(PLL) remains regulated but is not calibrated

(bit VREFPLL disable is logic 0). If bit VREFPLL disable is logic 1, Vref(PLL) is not regulated and fluctuates with VCC.

MAXIMUM CURRENT CONSUMPTION

Table 2 shows the typical and the maximum current consumption in the active mode and the three current saving modes

under the following conditions: IP3 HIGH mode (bit IP3 is logic 1), see Table 6; LNA gain is step 3 (bits LNA are logic 11),

see Table 12 and the PA output level is step 3 (bits PA are logic 11), see Table 15.

In the standby mode and in the inactive mode, pin Vref(PLL) is not powered (bit VREFPLL disable is logic 1) and the clock

output signal is disabled (bits clock divider ratio are logic 00).

2000 Aug 10

6

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