UAA2062 Просмотр технического описания (PDF) - Philips Electronics

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UAA2062

Analog cordless telephone IC

Philips Electronics 

Philips Semiconductors

Analog cordless telephone IC

Product specification

UAA2062

Other features

PLL VOLTAGE REGULATOR

Pin Vref(PLL) provides the internal supply voltage for the

RX and TX PLLs. It is regulated at 3 V. Pin VCC(AU)

provides the supply voltage input for the internal voltage

regulator. Two capacitors of 47 µF and 100 nF must be

connected to pin Vref(PLL) to filter and stabilize this

regulated voltage. The tolerance of the regulated voltage

is initially ±8% but is improved to ±4% after the internal

band gap voltage reference is adjusted via the

microcontroller.

The voltage regulator is always turned on. In the inactive

mode the calibration is turned off to reduce current

consumption. In this mode, the Vref(PLL) block supplies

300 µA to the microcontroller. The output drive capability

is 3 mA. The voltage regulator is able to supply the

microcontroller.

The local oscillator LO2 and the RX and TX phase

detectors are powered by the internal voltage regulator at

pin Vref(PLL). Therefore, the maximum input and output

level for most I/O pins (LO2I and LO2O) equals the

regulated voltage at pin Vref(PLL).

LOW-BATTERY DETECTOR

The low-battery detector measures the voltage level of the

VCC(AU) using a resistance divider and a comparator. One

input of the comparator is connected to VB, the other to the

middle point of the resistance divider.

The comparator has a built-in hysteresis to prevent

spurious switching. The precision of the detection depends

on the divider accuracy, the comparator offset and the

accuracy of the reference voltage VB. The output is

multiplexed at pin CDBDO. When the battery voltage level

is below the threshold voltage the output CDBDO is going

LOW.

Microcontroller serial interface

Pins DATA, CLK and EN provide a 3-wire unidirectional

serial interface for programming the reference counters,

the transmit and receive channel divider counters and the

control functions.

The interface consists of 18-bit shift registers connected to

a matrix of registers organized as 6 words of 18 bits. The

leading 15 bits include the data D14 to D0. The trailing

3 bits set up the address AD2 to AD0. The data is entered

with the most significant bit D14 first. The last bit is

bit AD0.

Pins DATA and CLK are used to load data into the shift

register. Figure 10 shows the timing required on all pins.

Data is clocked into the shift registers on negative clock

transitions.

The serial interface pins DATA, CLK and EN, are supplied

by Vref(PLL). Internal level shifters are provided after the

pins which allow the logic and registers to be internally

powered by VCC(AU).

The ESD protection diodes on these pins are connected to

VCC(AU). All the digital outputs (CDBDO and DATO) are

open-collector outputs.

handbook, full pagewidth

data bits (15)

DATA

D14

D13

tSU;DC

CLK

50%

50%

tHD;EC

tSU;CE

EN

50%

address bits (3)

D12

AD1

AD0

tEND

tw

Fig.10 Digital signals timing requirement.

data bits latched

MGR004

2000 Aug 10

12

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