CDB5126 Просмотр технического описания (PDF) - Cirrus Logic
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CDB5126 Datasheet PDF : 32 Pages
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CS5126
Simultaneous Sampling
The CS5126 offers four digital output signals,
SSH1, SSH2, TRKL, and TRKR which can be
used to control external sample/hold amplifiers
to achieve simultaneous sampling and/or reduce
sampling distortion.
Figure 7 shows the timing relationships for
SSH1, SSH2, TRKL, and TRKR. In the stereo
configuration shown in Figure 1 the CS5126
samples the left and right channels 180° out of
phase. Simultaneous sampling between the left
and right channels can be achieved as shown in
Figure 8a using the CS5126’s SSH2 output. The
external sample/hold will freeze the right chan-
nel analog signal as the CS5126 freezes the left
channel input at AINL. It will hold that signal
valid at AINR until the CS5126 begins a right
channel conversion. Once that conversion be-
gins, the sample/hold returns to the sample
mode. The acquisition time for the external sam-
ple/hold amplifier must not exceed the CS5126’s
minimum conversion time of 192 master clock
cycles (7.8µs for 48kHz stereo sampling).
AINL
S/H
AINR
SSH2
a. Standard Connections
S/H
AINL
SSH1
S/H
AINR
b. High-Slew Conditions
Figure 8. Simultaneous Sampling Connections
The CS5126’s sampling distortion with high-fre-
quency, high-amplitude input signals may be im-
proved if a low distortion sample/hold amplifier
is used as shown in Figure 8a. The right channel
input at AINR will appear as dc to the CS5126
resulting in no ac current flowing through the
internal MOS switches. Sampling distortion can
likewise be improved for both channels using
the SSH1 output as shown in Figure 8b. Simi-
L/R (i)
HOLD (i)
Internal
Status
SSH1 (o)
SSH2 (o)
Rch Convert
Lch Acq.
Acq. & Track
Acquire & Track
Lch Convert
Rch Acq.
Hold
Hold
Rch Convert
Lch Acq.
TRKL (o)
TRKR (o)
10
Figure 7. External Sampling Control Output Timing
DS32F1
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