PCD5002 Просмотр технического описания (PDF) - Philips Electronics
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PCD5002 Datasheet PDF : 48 Pages
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Philips Semiconductors
Advanced POCSAG and APOC-1 Paging
Decoder
Product specification
PCD5002
After reception of any broadcast message data the
PCD5002 continues to operate in the ‘cycle receive’ mode.
In the cycle receive mode the PCD5002 enables call
reception in only one programmed batch per cycle. Sync
word detection takes place from 2 bits before to 2 bits after
the expected sync word position of this batch. If the sync
word is not detected then the position of the current sync
word will be maintained and the ‘short fade recovery’
mode will be entered.
When a valid sync word is found user address codeword
detection takes place, as in normal POCSAG code.
Any following message codewords are received normally.
If a message extends into a subsequent batch containing
a batch zero identifier, then the batch zero identifier is
detected normally and message reception will continue.
Data reception is suspended after the programmed batch
until the same batch position in the next cycle.
The exception being when a received call continues into
the next batch.
In the short fade recovery mode the programmed data
receive batch will continue to be checked for user address
codewords. In addition the first codeword after the
programmed batch is checked for sync word or preamble.
When a valid sync word is detected the ‘cycle receive’
mode is re-entered, while detection of preamble causes
the device to switch to the ‘preamble receive’ mode. When
neither is found then the ‘transmitter off’ mode is entered.
In the transmitter off mode a time-out is set to a
pre-programmed duration. This time-out corresponds to
the maximum time between subsequent transmissions
(preamble to preamble).
The PCD5002 then checks the first batch of every cycle for
sync word or preamble. The programmed data receive
batch is ignored (unless it is batch 0).
Table 4 Synchronization window tolerance as a function
of bit rate
TIME FROM
LOSS OF SIGNAL
≤ 30 s
≤ 60 s
≤ 120 s
≤ 240 s
TOLERANCE
512
(bits/s)
1 200
(bits/s)
2 400
(bits/s)
4 bits
4 bits
4 bits
8 bits
4 bits
4 bits
8 bits
16 bits
4 bits
8 bits
16 bits
32 bits
Synchronization checking is performed over a window
ranging from ‘n’ bits before to ‘n’ bits after the expected
sync word position. The window tolerance ‘n’ depends on
the time since the ‘transmitter off’ mode was entered and
on the selected bit rate (see Table 4).
When a sync word is detected in this widened
synchronization window the PCD5002 enters the
‘batch zero identify’ mode. Time-out expiry before a sync
word has been detected causes the device to switch to the
‘long fade recovery’ mode.
Detection of preamble in the ‘transmitter off’ mode initiates
the preamble receive 2 mode. Operation in this mode is
identical to ‘preamble receive mode. Failure to detect
preamble for one batch period will cause the device to
switch back to the ‘transmitter off’ mode. This prevents
inadvertent loss of cycle synchronization due to spurious
signals resembling preamble.
The carrier detect mode is identical to the ‘carrier off’
mode in standard POCSAG operation. Upon first entry the
transmitter off time-out is started. The receiver is enabled
to receive one codeword in every 18 codewords to check
for sync word and preamble. This check is performed on
the last available 32 bits for every received bit.
The ‘preamble receive’ mode is entered if preamble is
detected. If a valid sync word is found the
‘batch zero detect’ mode is entered. If neither has been
detected and the time-out expires, then the
‘long fade recovery’ mode is entered.
The long fade recovery mode is intended to quickly
regain synchronization in fading conditions (not caused by
the transmitter switching off between transmissions) or
when having been out of range, while maintaining
acceptable battery economy.
Initially, the receiver is switched off until one cycle duration
after the last enabling in the ‘transmitter off’ mode.
The receiver is then enabled for a 2 codeword period in
which each contiguous group of 32 bits is tested for any
decodable POCSAG codeword (including sync word) and
preamble. Single-bit error correction is applied.
If a codeword is detected, the receiver enable period is
extended by another codeword duration and the above
test is repeated. This process continues while valid
codewords are received.
Detection of preamble will cause the device to switch to the
‘preamble receive’ mode, while sync word detection will
cause the device to switch to the ‘batch zero detect’ mode.
When neither is detected during the 2 codeword window or
any following 32-bit group, the receiver will be disabled.
1997 Jun 24
12
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