MAX5123(1999) Просмотр технического описания (PDF) - Maxim Integrated

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MAX5123
(Rev.:1999)

+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/°C Internal Reference

Maxim Integrated 

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

Pin Description

PIN NAME

FUNCTION

1

FB

Amplifier Inverting Sense Input (Analog Input)

2

OUT Analog Output Voltage. High impedance if part is in shutdown.

Reset Value Input (Digital Input).

3

RSTVAL 1: Connect to VDD to select midscale as the output reset value.

0: Connect to DGND to select 0V as the output reset value.

Power-Down Lockout (Digital Input).

4

PDL

1: Normal operation.

0: Disallows shutdown (device cannot be powered down).

5

CLR

Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the

DAC will cause it to exit a software shutdown state.

6

CS

Active-Low Chip-Select Input (Digital Input)

7

DIN

Serial Data Input. Data is clocked in on the rising edge of SCLK.

8

SCLK Serial Clock Input

9

DGND Digital Ground

10

DOUT Serial Data Output

11

UPO User-Programmable Output (Digital Output)

12

PD

Power-Down Input (Digital Input). Pulling PD high when PDL = VDD places the IC into shutdown with a maxi-

mum shutdown current of 20µA.

13

AGND Analog Ground

Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V

14

REF

(MAX5122) or +1.25V (MAX5123) nominal output, externally adjustable at REFADJ. In external reference

mode, disable the internal reference by pulling REFADJ to VDD and applying the external reference to REF.

15

REFADJ

Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to VDD when using an

external reference.

16

VDD

Positive Power Supply. Bypass with a 0.1µF capacitor in parallel with a 4.7µF capacitor to AGND.

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