MAX5123(1999) Просмотр технического описания (PDF) - Maxim Integrated
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MAX5123
(Rev.:1999)
(Rev.:1999)
Maxim Integrated
MAX5123 Datasheet PDF : 20 Pages
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+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
TIMING CHARACTERISTICS—MAX5123 (+3V)
(VDD = +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL = 5kΩ, CL = 100pF, output amplifier connected
in unity-gain, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Clock Period
tCP
SCLK Pulse Width High
tCH
150
ns
75
ns
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
tCL
tCSS
tCSH
75
ns
60
ns
0
ns
SDI Setup Time
tDS
60
ns
SDI Hold Time
tDH
0
ns
SCLK Rise to DOUT Valid
Propagation Delay Time
tDO1
CLOAD = 200pF
200
ns
SCLK Fall to DOUT Valid
Propagation Delay Time
SCLK Rise to CS Fall Delay Time
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
tDO2
tCS0
tCS1
tCSW
CLOAD = 200pF
200
ns
10
ns
75
ns
150
ns
Note 1: Accuracy is guaranteed by the following table:
VDD
Accuracy Guaranteed
(V)
From Code:
To Code:
5
16
4095
3
33
4095
Note 2: Offset is measured at the code closest to 10mV.
Note 2: The temperature coefficient is determined by the “box” method, in which the maximum ∆VOUT over the temperature range
is divided by ∆T and the typical reference voltage.
Note 4: Accuracy is better than 1.0LSB for VOUT = 10mV to (VDD - 180mV). Guaranteed by PSR test on end points.
Note 5: RLOAD = ∞and digital inputs are at either VDD or DGND.
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