Ultra-Low Leakage Monolithic CMOS
Analog Multiplexers
50%
+10V
VAH = 3.0V
ADDRESS
DRIVE (VA) 0V
VA
90%
tA
OUTPUT A
-10V
Figure 1. Access Time vs. Logic Level (High)
A2
A1
50Ω
A0
EN
+VAH
MAX328
GND
S1
S2
S2–S7
S8
OUT
±10V
±10V
PROBE
10MΩ 14pF
VAH = 3.0V
ADDRESS
VA
0V
DRIVE (VA)
OUTPUT
50%
50%
tOPEN
Figure 2. Break-Before-Make Delay (tOPEN)
A2
A1
50Ω
A0
EN
2.4V
MAX328
GND
S1
S2–S7
S8
OUT
1kΩ
+5V
VOUT
12.5pF
VAH = 3.0V
ENABLE DRIVE
50%
0V
90%
tON(EN)
OUTPUT
VA
90%
tOFF(EN)
A2
A1
A0
EN
50Ω
S1
+10V
MAX328
S2–S7
GND
OUT
1kΩ
12.5pF
Figure 3. Enable Delay (tON(EN), tOFF(EN))
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