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LH543601

256 × 36 × 2 Bidirectional FIFO

Sharp Electronics 

256 × 36 × 2 Bidirectional FIFO

LH543601

AC ELECTRICAL CHARACTERISTICS 1 (VCC = 5 V ± 10%, TA = 0°C to 70°C)

SYMBOL

DECRIPTION

–20

MIN MAX

–25

MIN MAX

–30

MIN MAX

–35

UNITS

MIN MAX

fCC

tCC

tCH

tCL

tDS

tDH

tES

tEH

tRWS

tRWH

tRQS

tRQH

tAS

tAH

tA

tACK

tOH

tZX

tXZ

tEF

tFF

tHF

tAE

Clock Cycle Frequency

—

50

—

40

—

33

— 28.5 MHz

Clock Cycle Time

20

—

25

—

30

—

35

—

ns

Clock HIGH Time

8

—

10

—

12

—

15

—

ns

Clock LOW Time

8

—

10

—

12

—

15

—

ns

Data Setup Time

10

—

12

—

13

—

15

—

ns

Data Hold Time

0

—

0

—

0

—

0

—

ns

Enable Setup Time

10.4 —

13

—

15

—

15

—

ns

Enable Hold Time

0

—

0

—

0

—

0

—

ns

Read/Write Setup Time

10.4 —

13

—

15

—

18

—

ns

Read/Write Hold Time

0

—

0

—

0

—

0

—

ns

Request Setup Time

12

—

15

—

18

—

21

—

ns

Request Hold Time

Address Setup Time 6

Address Hold Time 6

0

—

0

—

0

—

0

—

ns

12

—

15

—

18

—

21

—

ns

0

—

0

—

0

—

0

—

ns

Data Output Access Time

— 12.8 —

16

—

20

—

25

ns

Acknowledge Access Time

—

12

—

15

—

20

—

25

ns

Output Hold Time

2.0

—

2.0

—

2.0

—

2.0

—

ns

Output Enable Time, OE LOW to D0

– D35 Low-Z 2

1.5

—

2.0 — 3.0

— 3.0 —

ns

Output Disable Time, OE HIGH to

D0 – D35 High-Z 2

—

9

—

12

—

15

—

20

ns

Clock to EF Flag Valid (Empty Flag) — 17.6 —

22

—

25

—

30

ns

Clock to FF Flag Valid (Full Flag)

— 17.6 —

22

—

25

—

30

ns

Clock to HF Flag Valid (Half-Full)

— 17.6 —

22

—

25

—

30

ns

Clock to AE Flag Valid (Almost-

Empty)

—

16

—

20

—

25

—

30

ns

tAF

Clock to AF Flag Valid (Almost-Full) —

16

—

20

—

25

—

30

ns

tMBF

Clock to MBF Flag Valid (Mailbox

Flag)

—

12

—

15

—

20

—

25

ns

tPF

Data to Parity Flag Valid

— 13.6 —

17

—

20

—

25

ns

tRS

Reset/Retransmit Pulse Width 7

32/20 — 40/25 — 52/30 — 65/35 —

ns

tRSS

Reset/Retransmit Setup Time 3

16

—

20

—

25

—

30

—

ns

tRSH

Reset/Retransmit Hold Time 3

8

—

10

—

15

—

20

—

ns

tRF

Reset LOW to Flag Valid

tFRL

First Read Latency 4

tFWL

First Write Latency 5

—

28

—

35

—

40

—

45

ns

20

—

25

—

30

—

35

—

ns

20

—

25

—

30

—

35

—

ns

tBS

Bypass Data Setup

12

—

15

—

18

—

21

—

ns

tBH

Bypass Data Hold

3

—

5

—

5

—

5

—

ns

tBA

Bypass Data Access

—

18

—

20

—

25

—

30

ns

NOTES:

1. Timing measurements performed at ‘AC Test Condition’ levels.

2. Values are guaranteed by design; not currently production tested.

3. tRSS and/or tRSH need not be met unless a rising edge of CKA occurs while ENA is being asserted, or else a rising edge of CKB occurs while

ENB is being asserted.

4. tFRL is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data.

5. tFWL is the minimum first-read-to-first-write delay, following a full condtion, which is required to assure successful writing of data.

9

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