KM41C4000D Просмотр технического описания (PDF) - Samsung

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KM41C4000D

4M x 1Bit CMOS Dynamic RAM with Fast Page Mode

Samsung 

KM41C4000D, KM41V4000D

CMOS DRAM

NOTES

1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles

before proper device operation is achieved.

2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between

VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.

3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF.

4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.

If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.

5. Assumes that tRCD≥tRCD(max).

6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

7. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical

characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for

the duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min) then the cycle is a

read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-

ditions is satisfied, the condition of the data out is indeterminate.

8. Either tRCH or tRRH must be satisfied for a read cycle.

9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.

10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.

If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

11. These specifiecations are applied in the test mode.

12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

13. tOFF(MAX) defines the time at which the output achieves the open circuit condition and are not referenced to output voltage

level.

14. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.

15. For RAS-only refresh and burst CAS-before-RAS refresh mode, 1024(1K) cycle of burst refresh must be executed within

16ms before and after self refresh, in order to meet refresh specification.

16. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immedi-

ately before and after self refresh in order to meet refresh specification.

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