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IDT54FCT162344AT

FAST CMOS ADDRESS/CLOCK DRIVER

Integrated Device Technology 

IDT54/74FCT162344AT/CT/ET

FAST CMOS ADDRESS LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

VCC

7.0V

VIN

Pulse

Generator

V OUT

D.U.T.

500Ω

50pF

500Ω

RT

CL

SWITCH POSITION

Test

Switch

Open Drain

Disable Low

Closed

Enable Low

All Other Tests

Open

DEFINITIONS:

3069 lnk 09

CL= Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

3069 drw 04

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

DATA

INPUT

TIMING

INPUT

t SU

tH

3V

1.5V

0V

3V

1.5V

0V

LOW-HIGH-LOW

PULSE

tW

1.5V

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

t REM

3V

1.5V

0V

HIGH-LOW-HIGH

PULSE

1.5V

SYNCHRONOUS CONTROL

3069 drw 06

PRESET

CLEAR

CLOCK ENABLE

ETC.

tH

t SU

3V

1.5V

0V

3069 drw 05

PROPAGATION DELAY

SAME PHASE

INPUT TRANSITION

t PLH

OUTPUT

t PLH

OPPOSITE PHASE

INPUT TRANSITION

t PHL

t PHL

3V

1.5V

0V

V OH

1.5V

V OL

3V

1.5V

0V

OUTPUT SKEW - tSKn(o)

3069 drw 07

INPUT

OUTPUT 1

OUTPUT 2

tPLH1

tPHL1

tSK1(o)

tSK1(o)

tPLH2

tPHL2

3V

1.5V

0V

VOH

1.5V

VOL

VOH

1.5V

VOL

NOTE:

tSKn(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|

1. For tSK1(o) OUTPUT1 and OUTPUT 2 are in the same bank,

For tSK2(o) OUTPUT1 and OUTPUT 2 are in different banks on the

same part.

ENABLE AND DISABLE TIMES

ENABLE

CONTROL

INPUT

t PZL

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

t PZH

OUTPUT SWITCH

NORMALLY OPEN

HIGH

3.5V

1.5V

1.5V

0V

DISABLE

t PLZ

3V

1.5V

0V

3.5V

t PHZ

0.3V V OL

0.3V V OH

0V

3069 drw 08

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

5.6

7

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