HM-6508/883
Functional Diagram
A5
A
A6
LATCHED 5 GATED
A7
A8
ADDRESS
ROW
REGISTER
DECODER 32
A
A9
5
32 x 32
MATRIX
32
D
GATED COLUMN
A
DECODER
AND DATA I/O
Q
A
W
5
5
A
A
LATCHED ADDRESS
E
REGISTER
A0 A1 A2 A3 A4
NOTES:
1. All lines positive logic - active high.
2. Three-state buffers: A high → output active.
3. Address latches and gated decoders: Latch on falling edge of E and gate on falling edge of E.
6-70