SSD1811 Просмотр технического описания (PDF) - Solomon Systech

Номер в каталоге

Компоненты Описание

Список матч

SSD1811

LCD Segment / Common Driver with Controller

Solomon Systech  

VL2, V L3, VL4 and VL5

These are the LCD driving voltage levels. All these levels

are referenced to VDD.

They can be supplied externally or generated by the internal

bias divider, by turning on the output op-amp buffers option in

the Set Power Control Register command.

The potential relation of these pins are given as:

VDD > VL2 > VL3 > VL4 > VL5 > VL6

and with bias factor, a,

VL2 - VDD = 1/a * (VL6 - VDD)

VL3 - VDD = 2/a * (VL6 - VDD)

VL4 - VDD = (a-2)/a * (VL6 - VDD)

VL5 - VDD = (a-1)/a * (VL6 - VDD)

VL6

This pin is the most negative LCD driving voltage. It can be

supplied externally or generated by turning on the internal reg-

ulator option in the Set Power Control Register command.

VF

This pin is the input of the built-in voltage regulator for gen-

erating VL6.

When external resistor network is selected (IRS pulled low)

to generate the LCD driving level, VL6, two external resistors, R1

and R2, should be connected between VDD and VF, and VF and

VL6, respectively (see application circuit diagrams).

M/S

This pin is the master/slave mode selection input. When this

pin is pulled high, master mode is selected, which CL, M,

MSTAT and DOF signals will be output for slave devices.

When this pin is pulled low, slave mode is selected, which

CL, M, DOF are required to be input from master device and

MSTAT is high impedance.

CLS

This pin is the internal clock enable pin. When this pin is

pulled high, internal clock is enabled.

The internal clock will be disabled when it is pulled low, an

external clock source must be input to CL pin for normal opera-

tion.

C68/80

This pin is MCU parallel interface selection input. When the

pin is pulled high, 6800 series interface is selected and when the

pin is pulled low, 8080 series interface is selected.

If Serial Interface is selected (P/S pulled low), the setting of

this pin is ignored, but must be connected to a known logic (ei-

ther high or low).

P/S

This pin is serial/parallel interface selection input. When this

pin is pulled high, parallel interface mode is selected. When it is

pulled low, serial interface will be selected.

Note1: For serial mode, D0, D1, D2, D3, D4, D5, R/W/

(WR), E/(RD) is recommended to be connected to Vss.

Note2: Read Back operation is only available in parallel

mode.

HPM

This pin is the control input of High Power Current Mode.

The function of this pin is only enabled for High Power model

which required special ordering.

For normal models, High Power Mode is disabled and the

LCD driving characteristics are the same no matter this pin is

pulled High or Low.

Note: This pin must be pulled to either High or Low. Leaving

this pin floating is prohibited.

IRS

This is the input pin to enable the internal resistors network

for the voltage regulator. When this pin is pulled high, the internal

feedback resistors of the internal regulator for generating VL6 will

be enabled.

When it is pulled low, external resistors, R1 and R2, should

be connected to VDD and VF, and VF and VL6, respectively (see

application circuit diagrams).

ROW0 - ROW63

These pins provide the Common driving signals to the LCD

panel. See Table 3 on page 10 for the COM signal mapping in

different SSD181X members.

SEG0 - SEG131

These pins provide the LCD segment driving signals. The

output voltage level of these pins is VDD during sleep mode and

standby mode.

ICONS

There are two ICONS pins (pin12 and 136) on the chip. Both

pins output exactly the same signal. The reason for duplicating

the pin is to enhance the flexibility of the LCD layout.

NC

These are the No Connection pins. Nothing should be con-

nected to these pins, nor they are connected together. These

pins should be left open individually.

SSD181X Series

9

Rev 3.1

08/2001

SOLOMON

Share Link: