SSD1811 Просмотр технического описания (PDF) - Solomon Systech

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SSD1811

LCD Segment / Common Driver with Controller

Solomon Systech  

FUNCTIONAL BLOCK DESCRIPTIONS

Command Decoder and Command Interface

This module determines whether the input data is interpret-

ed as data or command. Data is directed to this module based

upon the input of the D/C pin.

If D/C pin is high, data is written to Graphic Display Data

RAM (GDDRAM). If it low, the input at D7-D0 is interpreted as a

Command and it will be decoded and be written to the corre-

sponding command register.

MPU Parallel 6800-series Interface

The parallel interface consists of 8 bi-directional data pins

(D7-D0), R/W(WR), D/C, E(RD), CS1 and CS2. R/W(WR) input

high indicates a read operation from the Graphic Display Data

RAM (GDDRAM) or the status register. R/W(WR) input Low in-

dicates a write operation to Display Data RAM or Internal Com-

mand Registers depending on the status of D/C input. The

E(RD) input serves as data latch signal (clock) when high provid-

ed that CS1 and CS2 are low and high respectively. Refer to Fig-

ure 11 on page 27 for Parallel Interface Timing Diagram of 6800-

series microprocessors.

In order to match the operating frequency of the GDDRAM

with that of the MCU, some pipeline processing is internally per-

formed which requires the insertion of a dummy read before the

first actual display data read. This is shown in Figure 3.

MPU Parallel 8080-series interface

The parallel interface consists of 8 bi-directional data pins

(D7-D0), E(RD), R/W(WR), D/C, CS1 and CS2. E(RD) input

serves as data read latch signal (clock) when low provided that

CS1 and CS2 are low and high respectively. Whether it is display

data or status register read is controlled by D/C. R/W(WR) input

serves as data write latch signal(clock) when high provided that

CS1 and CS2 are low and high respectively. Whether it is display

data or command register write is controlled by D/C. Refer to

Figure 12 on page 28 for Parallel Interface Timing Diagram of

8080-series microprocessor.

Similar to 6800-series interface, a dummy read is also re-

quired before the first actual display data read.

MPU Serial interface

The serial interface consists of serial clock SCK (D6), serial

data SDA (D7), D/C, CS1 and CS2. SDA is shifted into a 8-bit

shift register on every rising edge of SCK in the order of D7,D6,...

D0. D/C is sampled on every eighth clock to determine whether

the data byte in the shift register is written to the Display Data

RAM or command register at the same clock.

R/W(WR)

E ( R D)

data bus

N

write column address

dummy read

n

data read1

n+1

data read 2

n+2

data read 3

Figure 3 Display Data Read Back Procedure - Insertion of Dummy Read

SSD181X Series

11

Rev 3.1

08/2001

SOLOMON

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