KE5B256B1 Просмотр технического описания (PDF) - KAWASAKI MICROELECTRONICS

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KE5B256B1

ADDRESS PROCESSOR

KAWASAKI MICROELECTRONICS 

Address Processor KE5B256B1

Specifications (cont'd)

Ports

Sequence

reset

Search result

output pins

Cycle time

Input Port

· Input data block width is selectable (32, 16, or 8 bits)

(Key data input)

· Multi-channel:

IP sequence of 2 channels (A/B) can be defined.

Number of start sequence can be selected.

Input Port sequence

Maximum 8-stepinput sequence configuration and data

(IP Sequence)

formatting functions.

· Cut Through:

Any block selectable among 64 blocks in data stream

· Data Accumulation :

Most recent 64 bits can be temporarily stored

(Accumulation Buffer & Sub-accumulation Buffer)

· Search WindowSet:

Key data selectable with 32-bit width among 64 bits of

accumulateddata starting from n (n=0-3, n byte shift) byte

· Mask operation by bit

· Any segment can be searchedin any order.

Output Port

· 32 bits

(Search result output) · Multi-channel

OP sequence of 2 channels (A/B) can be defined.

Number of start sequence can be selected.

Output Port sequence

Maximum 8-stepoutput sequence configuration

(OP Sequence)

· Search key data:

Key data after data formatting used in the IP sequence

(CMP0 - CMP7 register)

· Hit status:

Hit, multi-hit, usedchannel (HSTAT register)

· Hit address:

Hit entry address with the highest priority (HHA register)

· Contents of hit address (MEMHHA register)

* Hit status can be output in combination with other search results

CPU Port

· 16-bit data, 8-bit address

· Command execution

· Register Read/Write

· SQRST_ (Pin)

· SSQRST command (from CPUPort)

· HO_: Results of each search operation

· SH0_, SH1_: Intermediate search results of specifiedstep in the IP sequence

80ns

I/F

LVTTL compatible

Supply voltage

Package

Technology

3.3V ± 0.3V

144-pin PQFP

0.5µ m CMOS

1-3

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