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KE5B256B1

ADDRESS PROCESSOR

KAWASAKI MICROELECTRONICS 

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Address Processor KE5B256B1

1.2 Functional Overview

The KE5B256B1 (Address Processor: AP) provides the

best solution to the fast and complex "Address Filtering"

requirements of today's internetworking equipment with

the following outstanding functions.

(1) Flexible search data table definition answering to vari-

ous protocols.

• The entry size is configurable from 32 bits to 256

bits.

• The search operation of any width key data can be

performed with data at any position in the table.

• All the CAM area can be accessed as RAM.

(2) 3-port architecture

• Optimized functionality for each port provides

fast data processing.

(3) Programmable input data formatting and search se-

quence

• The input data width can be selected as 32, 16, or

8 bits.

• Definition of data input and search start position.

• Masking by bit is possible.

• Search window set by byte unit.

• Maximum 8 step search sequence definition

to any column of the table.

(4) Programmable output sequence

• Output sequence definition of any search

result.

• Output sequence definition of any column of

the hit entry.

(5) Multi-channel sequence

• A maximum of 16 kinds of IP sequences and OP

sequences can be defined by indicating the channel/

number of the start sequence.

(6) Cascading

• No additional logic is required.

• A cascaded table acts as one integral search data.

(7) Commands

• Useful commands for the search table mainte-

nance

1.3 Specifications

CAM core

Capacity

Access to table entry

Config uration

(Entry size)

Cas cading

Search Operation

Result Output

256 kbits

Random access to all data

(RAM, CAM s ubs titution)

Configurable to control the entry width from 32 bits to 256 bits

in units of 32 bits

• 32 bits x 8,192 entries

• 64 bits x 4,096 entries

• 96 bits x 2,728 entries

• 128 bits x 2,048 entries

• 160 bits x 1,636 entries

• 192 bits x 1,364 entries

• 224 bits x 1,168 entries

• 256 bits x 1,024 entries

Up to 32 devices (adds table depth)

• Via CPU Port

• Via Input Port (automatic)

• Masking by bit

• Search operation by table segment (32 bits)

• AND search for more than 32 bits of data

• Hit accumulation using Access Bit

• Via CPU Port

• Via Output Port (automatic)

• Hit result pin (HO_)

• Intermediate search result pins (SH0_, SH1_)

• Hit

• Hit address

• Entry data of hit address

• Ke y data use d in se arch o pe ratio n

1-2

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