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W83195R-08

150MHZ 4-DIMM CLOCK

Winbond 

W83195R-08

5.3 I2C Control Interface

SYMBOL

PIN

*SDATA

27

*SDCLK

28

PRELIMINARY

I/O

FUNCTION

I/O Serial data of I2C 2-wire control interface with internal

pull-up resistor.

IN Serial clock of I2C 2-wire control interface with

internal pull-up resistor.

5.4 Fixed Frequency Outputs

SYMBOL

PIN

REF0 / PCI_STOP#

3

REF1 / *FS2

2

24MHz / *FS0

30

48MHz / *FS1

29

I/O

FUNCTION

I/O 14.318MHz reference clock. This REF output is the

stronger buffer for ISA bus loads.

Halt PCICLK(0:4) clocks at logic 0 level, when input

low (In mobile mode. MODE=0)

I/O 14.318MHz reference clock.

Latched input for FS2 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

I/O 24MHz output clock.

Latched input for FS1 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

I/O 48MHz output for USB during normal operation.

Latched input for FS0 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

5.5 Power Pins

SYMBOL

Vddq1

VddL1

VddL2

Vddq2

Vddq3

Vddq4

Vss

PIN

FUNCTION

1

Power supply for Ref [0:1] crystal and core logic.

56

Power supply for IOAPIC output, either 2.5V or 3.3V.

50

Power supply for CPUCLK_F & CPUCLK[1:2], either

2.5V or 3.3V.

7,15

Power supply for PCICLK_F, PCICLK[0:5], 3.3V.

20,37,45

Power supply for SDRAM_F & SDRAM[0:15], and CPU

PLL core, nominal 3.3V.

31

Power for 24 & 48MHz output buffers and fixed PLL

core.

4,10,23,26,34,42,48, Circuit Ground.

53

Publication Release Date: Mar. 1999

-4-

Revision 0.30

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