W83195R-08 Просмотр технического описания (PDF) - Winbond
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W83195R-08 Datasheet PDF : 18 Pages
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W83195R-08
5.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kΩ pull-up
5.1 Crystal I/O
PRELIMINARY
SYMBOL
Xin
Xout
PIN
I/O
FUNCTION
5
IN Crystal input with internal loading capacitors and
feedback resistors.
6
OUT Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL
CPUCLK_F
CPUCLK1
CPU_STOP#
IOAPIC0
IOAPIC_F
SDRAM [ 0:15]
PCICLK_F/
*MODE
PCICLK0/*FS3
PCICLK [ 1:5 ]
BUFFER IN
SDRAM_F
PIN
52
51
47
55
54
18,19,21,22,24
,25,32,33,35,
36,38,39,40,41
,43,44
8
9
11,12,13,14,16
17
46
I/O
OUT
OUT
IN
OUT
OUT
OUT
I/O
I/O
OUT
IN
O
FUNCTION
Free running CPU clock. Not affected by
CPU_STOP#
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
Powered by VddL2. Low if CPU_STOP# is low.
This asynchronous input halts CPUCLK1,IOAPIC &
SDRAM(0:12) at logic “0” level when driven low.
High drive buffered output of the crystal, and is
powered by VddL1.
Free running IOAPIC clock, and not affected by
CPU_STOP#
SDRAM clock outputs. Fanout buffer outputs from
BUFFER IN pin.(Controlled by chipset)
Free running PCI clock during normal operation.
Latched Input. Mode=1, Pin 2 is REF0; Mode=0,
Pin2 is PCI_STOP#
Low skew (< 250ps) PCI clock outputs.
Latched input for FS3 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Low skew (< 250ps) PCI clock outputs. Synchronous
to CPU clocks with 1-48ns skew(CPU early).
Inputs to fanout for SDRAM outputs.
Free running SDRAM clock, and not affected by
CPU_STOP#
Publication Release Date: Mar. 1999
-3-
Revision 0.30
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