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PVG610

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PVG610

Data Sheet

Revision History

Date Released Release

Reason for Revision

21-June-2007 002-F

1. Pin list in chapter 2.2: E6 SPARE 0 is

corrected to A6 SPARE 0

2. Chapter 8.1 Absolute Maximum Rating:

Junction temperature is -40 to 125°C

3. Updated fig. 106

4. Dual DAC DC Specification, Power dissipation

update in 6.4.3.2

5. Added section 5.4 System Clock Mode

6. Timing diagrams and tables in chapter 6

updated

18-July-2007

002-F1

1. Number of clock cycles between Tx/Rx Sync

and Tx/Rx ACM is changed to 2 (chapter 6.2.6)

2. Updated SPI Diagram 6.3.2

19-sep-2007

002-G

1. Max sampling rate of Envelope ADC

corrected to 80Msamples/sec (chapter 6.4.4)

2. Power consumption values added in 8.5

3. Description for Watch-dog mechanism added

in 3.7.3

18-oct-2007

002-G1

1. LIU power consumption update (8.5.2)

2. Update Thermal resistance parameter

23-Dec-2007

002-H

1. Signal direction of AK15 corrected to Output

(2.2)

2. XPIC slave power consumption added (8.5.1)

3. Location of RX_ACM signal corrected (6.2.6)

4. TBI Interface is removed

5. AFE spec updated (6.4)

6. HS mode in I2C removed (6.3.3)

02-April-2008

002-H2

1. Updating LIU power consumption (8.5.3)

2. MRC configuration removed (6.6)

23-June-2008

002-H4

1. Remove Boot process description (5.3.1).

2. Rise/fall time parameters added to 6.2.2.1.

3. Update PDH MCLK reference clock

frequency.

10-Nov-2008

002-H5

1. Max DDS CLK frequency is 112MHz (6.2.6)

2. Update Figure 76

3. Update operating conditions for VDD1P2 (8.2)

Comments

Provigent, Confidential

2

PVG610A_DSH_002_I3

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