Timing Diagrams
tF
SDA
SCL
tHD;STA
START
tR
tLOW
tSU;STA
tHIGH
tHD;DAT
TSU;DAT
tHD;STA
REPEATED
START
Figure 5. I2C Interface Timing for Fast and Slow Modes
tBUF
tHD;STO
STOP START
tFDA
tRDA
tSU;DAT
SDAH
tSU;STA
tRCL1
tFCL
tRCL
SCLH
tHD;STA
tLOW
tHIGH
tHD;DAT
REPEATED
START
note A
REPEATED
START
STOP
tSU;STO
= MCS Current Source Pull-up
= RP Resistor Pull-up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 6. I2C Interface Timing for High-Speed Mode
© 2008 Fairchild Semiconductor Corporation
9
FAN5355 • Rev. 1.0.4
www.fairchildsemi.com