FAN5355 Просмотр технического описания (PDF) - Fairchild Semiconductor
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FAN5355 Datasheet PDF : 27 Pages
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Pin Configuration
A1
A2
A3
A3
A2
A1
B1
B2
B3
B3
B2
B1
C1
C2
C3
C3
C2
C1
D1
D2
D3
D3
D2
D1
Top View
Bottom View
Figure 2. WLCSP- 12, 2.23x1.46mm
PVIN 1
10 SW
AVIN 2
SDA 3
SCL 4
PAD
AGND
9 PGND
8 AGND
7 EN
VSEL 5
6 VOUT
Top View
Figure 3. MLP10, 3x3mm
Pin Definitions
Pin #
WLCSP MLP
Name Description
A1, B1
A2
9
PGND
Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB. The
connection from this pin to the bottom of CIN should be as short as possible.
10
SW Switching Node. Connect to output inductor.
A3
1
PVIN
Power Input Voltage. Connect to input power source. The connection from this pin to CIN should be as
short as possible.
Sync. When toggling and SYNC_EN bit is HIGH, the regulator synchronizes to the frequency on this pin.
B2
N/A
SYNC In PWM mode, when this pin is statically LOW or statically HIGH, or when its frequency is outside of the
specified capture range, the regulator’s frequency is controlled by its internal 3MHz clock.
B3
2
AVIN
Analog Input Voltage. Connect to input power source as close as possible to the input bypass
capacitor.
C1
8, PAD
AGND
Analog GND. This is the signal ground reference for the IC. All voltage levels are measured with respect
to this pin.
C2
7
EN
Enable. When this pin is HIGH, the circuit is enabled. When LOW, quiescent current is minimized. This
pin should not be left floating.
C3
3
SDA SDA. I2C interface serial data.
D1
6
VOUT
Output Voltage Monitor. Tie this pin to the output voltage. This is a signal input pin to the control circuit
and does not carry DC current.
D2
5
VSEL
Voltage Select. When HIGH, VOUT is set by VSEL1. When LOW, VOUT is set by VSEL0. This behavior
can be overridden through I2C register settings. This pin should not be left floating.
D3
4
SCL SCL. I2C interface serial clock.
Note:
7. All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum
quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I2C control is unused, tie SDA and SCL to AVIN.
© 2008 Fairchild Semiconductor Corporation
3
FAN5355 • Rev. 1.0.4
www.fairchildsemi.com
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