VPC3201C Просмотр технического описания (PDF) - Micronas

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VPC3201C

VPC3205C, VPC3215C Video Processor Family

Micronas 

VPC 3205C, VPC 3215C

PRELIMINARY DATA SHEET

I2C Sub- Number Mode

address of bits

h’28 16

w/r

h’29 16

w/r

h’22 16

w/r

Function

AVO START:

bit[10:0]

bit[11]

bit[12] 0/1

bit[13] 0/1

bit[15:14] –2..1

AVO STOP:

bit[10:0]

bit[15:11]

bit[11] 0/1

bit[13:12]

00

01

10

11

bit[14] 0/1

bit[15] 0/1

NEWLINE:

bit[10:0]

bit[12:11]

bit[13]

bit[15:14]

Default Name

AVO START defines the beginning of the

AVO signal

in respect to the value of the sync counter.

reserved (set to 0)

vertical window disable/enable

vertical window 312/262 lines

vertical window interlace offset

60 AVSTRT

VERWIN

AVO STOP defines the end of the AVO

signal in respect to the value of the

sync counter.

reserved for test picture generation

(set to 0 in normal operation)

disable/enable test pattern generator

luma output mode:

Y = ramp (240 ... 17)

Y = 16

Y = 90

Y = 240

chroma output: 422/411 mode

chroma output: pseudo color bar/zero

if LMODE = 0

0 AVSTOP

0 COLBAREN

0 LMODE

0 M411

0 CMODE

NEWLINE defines the readout start of the

next line inrespect to the value of the sync

counter. The value of this register must be

greater than 31 for correct operation and

should be identical to AVOSTART (recom-

mended). In case of 1H-bypass mode for

scaler block, NEWLINE has no function.

reserved (set to 0)

vertical free run mode enabled, the vertical

frequency is selected via VERWIN (h’28)

reserved (set to 0)

50 NEWLIN

0 FLW

20

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