VPC3201C Просмотр технического описания (PDF) - Micronas

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VPC3201C

VPC3205C, VPC3215C Video Processor Family

Micronas 

PRELIMINARY DATA SHEET

VPC 3205C, VPC 3215C

2.8. Video Sync Processing

Fig. 2–12 shows a block diagram of the front-end sync

processing. To extract the sync information from the

video signal, a linear phase lowpass filter eliminates all

noise and video contents above 1 MHz. The sync is

separated by a slicer; the sync phase is measured. A

variable window can be selected to improve the noise

immunity of the slicer. The phase comparator mea-

sures the falling edge of sync, as well as the integrated

sync pulse.

The sync phase error is filtered by a phase-locked loop

that is computed by the FP. All timing in the front-end is

derived from a counter that is part of this PLL, and it

thus counts synchronously to the video signal.

A separate hardware block measures the signal back

porch and also allows gathering the maximum/mini-

mum of the video signal. This information is processed

by the FP and used for gain control and clamping.

For vertical sync separation, the sliced video signal is

integrated. The FP uses the integrator value to derive

vertical sync and field information.

The information extracted by the video sync process-

ing is multiplexed onto the hardware front sync signal

(FSY) and is distributed to the rest of the video pro-

cessing system. The format of the front sync signal is

given in Fig. 2–13.

The data for the vertical deflection, the sawtooth, and

the East-West correction signal is calculated by the

VPC 32xx. The data is buffered in a FIFO and trans-

ferred to the back-end IC DDP 3300A by a single wire

interface.

Frequency and phase characteristics of the analog

video signal are derived from PLL1. The results are fed

to the scaler unit for data interpolation and orthogonal-

ization and to the clock synthesizer for line-locked

clock generation. Horizontal and vertical syncs are

latched with the line-locked clock.

video

input

lowpass

1 MHz

&

syncslicer

horizontal

sync

separation

phase

comparator

&

lowpass

counter

PLL1

front

sync

generator

clamp &

signal

meas.

frontend

timing

clock

synthesizer

syncs

clamping, colorkey, FIFO_write

vertical

sync

separation

Sawtooth

Parabola

Calculation

FIFO

Fig. 2–12: Sync separation block diagram

vertical

serial

data

front sync

skew

vblank

field

clock

H/V syncs

vertical

E/W

sawtooth

input

analog

video

FSY

F0 F1

(not in scale)

Fig. 2–13: Front sync format

Micronas

F1

skew

LSB

F0 reserved

skew not

MSB used

F

V

V: vertical sync

Parity

0 = off

1 = on

F: field #

0 = field 1

1 = field 2

15

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