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CXB1454R

VGA/SVGA/XGA 24bit Receiver

Sony Semiconductor 

CXB1454R

CLKPOL Pin Control

The CLKPOL pin is used to select the SFTCLK trigger edge. (See Table 8.)

The CLKPOL pin is open High TTL input.

Table 8. SFTCLK Polarity

CLKPOL

L

H

Receiver operation trigger

Rising edge

Falling edge

PANEL1 and 0 Pin Control

The PANEL1 and 0 pins are used to select the panel mode. (See Table 9.)

For the normal use, the all frequencies of SFTCLK (25MHz to 65MHz) can be covered by fixing both PANEL1

and 0 to High.

The PANEL1 and 0 pins are open High TTL inputs.

Table 9. Panel Mode

PANEL1 PANEL0 Supporting panel size

L

L

VGA (640 × 480)

L

H

SVGA (800 × 600)

H

L

XGA (1024 × 768)

H

H

VGA to XGA

Shift clock

25MHz

40MHz

65MHz

25MHz to 65MHz

Serial rate

750Mbps

1200Mbps

1950Mbps

750Mbps to 1950Mbps

Test Pin Control

The TESTEXN, TESTDT and TESTSB pins are for test only. Select normal mode. (See Table 10.)

The TESTEXN, TESTDT and TESTSB pins are open High, TTL inputs.

Table 10. Test Mode

TESTEXN

L

H

TESTDT

X

H

TESTSB

X

H

Operation mode

Test mode

Normal mode

LOS Pin Output

The LOS pin shows the absence of proper level of SDATA signal. The LOS pin is High when the connector is

disconnected or the transmitter is idle.

The LOS pin is TTL output.

–9–

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