FW323-05 Просмотр технического описания (PDF) - Agere -> LSI Corporation
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FW323-05 Datasheet PDF : 152 Pages
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FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol*
Type
Description
79
PCI_AD[3]
80
PCI_AD[2]
81
VSS
82
VDD
83
PCI_AD[1]
84
PCI_AD[0]
85
PCI_VIOS
86
CONTENDER
87
PC2
88
PC1
89
PC0
90
LKON
91
LPS
92
NC
93
VDD
94
CPS
95
VSSA
96
VDDA
97
TPB2-
98
TPB2+
99
TPA2-
100
TPA2+
I/O
I/O
—
—
I/O
I/O
—
I
I
O
O
—
—
I
—
—
Analog I/O
Analog I/O
PCI Address/Data Bit.
PCI Address/Data Bit.
Ground.
Power.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Signaling Indicator. (5 V or 3.3 V.)
Contender. On hardware reset, this input sets the
default value of the CONTENDER bit indicated during
self-ID. This bit can be programmed by tying the signal
to VDD (high) or to ground (low).
Power-Class Indicators. On hardware reset, these
inputs set the default value of the power class indicated
during self-ID. These bits can be programmed by tying
the signals to VDD (high) or to ground (low).
Link On. Signal from the internal PHY core to the
internal link core. This signal is provided as an output
for use in legacy power management systems.
Link Power Status. Signal from the internal link core to
the internal PHY core. LPS is provided as an output for
use in legacy power management systems.
No Connect.
Power.
Cable Power Status. CPS is normally connected to the
cable power through a 400 kΩ resistor. This circuit
drives an internal comparator that detects the presence
of cable power. This information is maintained in one
internal register and is available to the LLC by way of a
register read (see IEEE 1394a-2000, Standard for a
High Performance Serial Bus (Supplement)).
Analog Circuit Ground. All VSSA signals should be
tied together to a low-impedance ground plane.
Analog Circuit Power. VDDA supplies power to the
analog portion of the device.
Port 2, Port Cable Pair B. TPB2± is the port B connec-
tion to the twisted-pair cable. Board traces from each
pair of positive and negative differential signal pins
should be kept matched and as short as possible to the
external load resistors and to the cable connector.
Port 2, Port Cable Pair A. TPA2± is the port A connec-
tion to the twisted-pair cable. Board traces from each
pair of positive and negative differential signal pins
should be kept matched and as short as possible to the
external load resistors and to the cable connector.
* Active-low signals within this document are indicated by an N following the symbol names.
16
Agere Systems Inc.
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